Balaji Venu
Balaji Venu
Verified email at arm.com
Title
Cited by
Cited by
Year
A triple core lock-step (TCLS) ARM® Cortex®-R5 processor for safety-critical and ultra-reliable applications
X Iturbe, B Venu, E Ozer, S Das
2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016
472016
Multi-core processors-an overview
B Venu
arXiv preprint arXiv:1110.3535, 2011
362011
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU
X Iturbe, B Venu, E Ozer
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2016
262016
Addressing functional safety challenges in autonomous vehicles with the arm TCL S architecture
X Iturbe, B Venu, J Jagst, E Ozer, P Harrod, C Turner, J Penton
IEEE Design & Test 35 (3), 7-14, 2018
162018
The Arm triple core lock-step (TCLS) processor
X Iturbe, B Venu, E Ozer, JL Poupat, G Gimenez, HU Zurek
ACM Transactions on Computer Systems (TOCS) 36 (3), 1-30, 2019
122019
A triple core lock-step ARM Cortex-R5 processor for safety-critical and ultra-reliable applications
X Iturbe, B Venu, E Ozer, S Das
IEEE DSN, 2016
102016
A fail-functional automotive CPU subsystem architecture for mitigating single point of failures
B Venu, E Ozer, X Iturbe, A Robinson
IEEE International Workshop on Automotive Reliability and Test, 2017
52017
Device, system and process for redundant processor error detection
E Ozer, X Iturbe, V Balaji
US Patent 10,628,277, 2020
42020
Error correlation prediction in lockstep processors for safety-critical systems
E Ozer, B Venu, X Iturbe, S Das, S Lyberis, J Biggs, P Harrod, J Penton
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
42018
Formal verification methodology considerations for network on chips
B Venu, A Singh
Proceedings of the International Conference on Advances in Computing …, 2012
42012
Self-testing in a processor core
V Balaji, KY Johar, M Bonino
US Patent 10,331,531, 2019
32019
Apparatus and method for checking output data during redundant execution of instructions
E Özer, V Balaji, X Iturbe, AJ Penton
US Patent 10,303,566, 2019
22019
Handling errors in buffers
V Balaji, ML Boettcher, M Eyole
US Patent 11,113,164, 2021
12021
Failure estimation in circuits
R Jeyapaul, V Balaji
US Patent 10,747,601, 2020
12020
Error recovery for intra-core lockstep mode
ML Boettcher, M Eyole, V Balaji
US Patent App. 16/641,377, 2020
12020
Vulnerability determination in circuits
V Balaji, R Jeyapaul, X Iturbe, MJ Horsnell, DM Gilday
US Patent 10,523,186, 2019
12019
Targeted recovery process
V Balaji, X Iturbe, E Özer
US Patent 10,185,635, 2019
12019
Error protection
E Özer, V Balaji
US Patent 10,108,486, 2018
12018
A" high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress
X Iturbe, B Venu, J Penton, E Ozer
Proceedings of the 2017 International Conference on Compilers, Architectures …, 2017
12017
An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults
A Narang, B Venn, S Khursheed, P Harrod
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021
2021
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