| Exploiting errors for efficiency: A survey from circuits to applications P Stanley-Marbell, A Alaghi, M Carbin, E Darulova, L Dolecek, ... ACM Computing Surveys (CSUR) 53 (3), 1-39, 2020 | 69 | 2020 |
| Design of approximate circuits by fabrication of false timing paths: The carry cut-back adder V Camus, M Cacciotti, J Schlachter, C Enz IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018 | 29 | 2018 |
| Combining structural and timing errors in overclocked inexact speculative adders X Jiao, V Camus, M Cacciotti, Y Jiang, C Enz, RK Gupta Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 13 | 2017 |
| Hardware acceleration of HDR-image tone mapping on an FPGA-CPU platform through high-level synthesis M Cacciotti, V Camus, J Schlachter, A Pezzotta, C Enz 2018 31st IEEE International System-on-Chip Conference (SOCC), 158-162, 2018 | 9 | 2018 |
| ASIC Design for Miniaturized Insect Eye-Inspired Image Processing System M Cacciotti EPFL, 2015 | | 2015 |
| Group ID U12701 Affiliated authors Beckers, Arnout DM Bold, A Boukhayma, M Briki, M Cacciotti, A Caizzone, V Camus, ... | | |
Vincent CamusEcole Polytechnique Fédérale de Lausanne (EPFL), SwitzerlandBestätigte E-Mail-Adresse bei alumni.epfl.ch
