Wei Hu
Wei Hu
University of California, San Diego & Northwestern Polytechnical University
Verified email at nwpu.edu.cn - Homepage
Title
Cited by
Cited by
Year
Information flow isolation in I2C and USB
J Oberg, W Hu, A Irturk, M Tiwari, T Sherwood, R Kastner
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 254-259, 2011
702011
Register transfer level information flow tracking for provably secure hardware design
A Ardeshiricham, W Hu, J Marxen, R Kastner
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
672017
Detecting hardware trojans with gate-level information-flow tracking
W Hu, B Mao, J Oberg, R Kastner
Computer 49 (8), 44-52, 2016
622016
Theoretical fundamentals of gate level information flow tracking
W Hu, J Oberg, A Irturk, M Tiwari, T Sherwood, D Mu, R Kastner
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
492011
Theoretical analysis of gate level information flow tracking
J Oberg, W Hu, A Irturk, M Tiwari, T Sherwood, R Kastner
Design Automation Conference, 244-247, 2010
352010
On the complexity of generating gate level information flow tracking logic
W Hu, J Oberg, A Irturk, M Tiwari, T Sherwood, D Mu, R Kastner
IEEE Transactions on Information Forensics and Security 7 (3), 1067-1080, 2012
332012
Energy-efficient border intrusion detection using wireless sensors network
T Yang, D Mu, W Hu, HX Zhang
EURASIP Journal on Wireless Communications and Networking 2014 (1), 1-12, 2014
302014
Gate-level information flow tracking for security lattices
W Hu, D Mu, J Oberg, B Mao, M Tiwari, T Sherwood, R Kastner
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014
262014
A bottom-up approach to verifiable embedded system information flow security
D Mu, W Hu, B Mao, B Ma
IET information security 8 (1), 12-17, 2013
202013
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking
W Hu, A Becker, A Ardeshiricham, Y Tai, P Ienne, D Mu, R Kastner
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
192016
Property specific information flow analysis for hardware security verification
W Hu, A Ardeshiricham, MS Gobulukoglu, X Wang, R Kastner
Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018
182018
Clepsydra: Modeling timing flows in hardware designs
A Ardeshiricham, W Hu, R Kastner
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 147-154, 2017
182017
Towards property driven hardware security
W Hu, A Althoff, A Ardeshiricham, R Kastner
2016 17th International Workshop on Microprocessor and SOC Test and …, 2016
142016
Quantifying timing-based information flow in cryptographic hardware
B Mao, W Hu, A Althoff, J Matai, J Oberg, D Mu, T Sherwood, R Kastner
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 552-559, 2015
132015
Enforcing information flow guarantees in reconfigurable systems with mix-trusted IP
R Kastner, J Oberg, W Huy, A Irturk
Proceedings of the International Conference on Engineering of Reconfigurable …, 2011
132011
Expanding gate level information flow tracking for multilevel security
W Hu, J Oberg, J Barrientos, D Mu, R Kastner
IEEE Embedded Systems Letters 5 (2), 25-28, 2013
122013
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design
B Mao, W Hu, A Althoff, J Matai, Y Tai, D Mu, T Sherwood, R Kastner
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2018
112018
Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans
W Hu, L Zhang, A Ardeshiricham, J Blackstone, B Hou, Y Tai, R Kastner
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 707-713, 2017
102017
Proportional delay differentiation service and load balancing in web cluster systems
A Gao, H Zhou, Y Hu, D Mu, W Hu
2010 INFOCOM IEEE Conference on Computer Communications Workshops, 1-2, 2010
102010
Examining the consequences of high-level synthesis optimizations on power side-channel
L Zhang, W Hu, A Ardeshiricham, Y Tai, J Blackstone, D Mu, R Kastner
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
82018
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