Formalization of laplace transform using the multivariable calculus theory of HOL-light HT Syeda, O Hasan International Conference on Logic for Programming Artificial Intelligence …, 2013 | 43 | 2013 |
Do you have space for dessert? A verified space cost semantics for CakeML programs A Gómez-Londoño, J Åman Pohjola, HT Syeda, MO Myreen, YK Tan Proceedings of the ACM on Programming Languages 4 (OOPSLA), 1-29, 2020 | 25 | 2020 |
Program verification in the presence of cached address translation HT Syeda, G Klein Interactive Theorem Proving: 9th International Conference, ITP 2018, Held as …, 2018 | 17 | 2018 |
Reasoning about Translation Lookaside Buffers HT Syeda, G Klein International Conference on Logic for Programming Artificial Intelligence …, 2017 | 15 | 2017 |
Formal Reasoning Under Cached Address Translation HT Syeda, G Klein Journal of Automated Reasoning, 2020 | 13 | 2020 |
Formally Verifying Transfer Functions of Linear Analog Circuits HT Syeda, O Hasan IEEE Design & Test, 2017 | 8* | 2017 |
Pancake: verified systems programming made sweeter JÅ Pohjola, HT Syeda, M Tanaka, K Winter, TW Sau, B Nott, TT Ung, ... Proceedings of the 12th Workshop on programming languages and operating …, 2023 | 5 | 2023 |
Low-level program verification under cached address translation H Syeda UNSW Sydney, 2019 | 4 | 2019 |
Formal verification of continuous models of analog circuits HT Syeda, O Hasan Frontiers in Analog CAD, Poster Paper, 2013 | 2* | 2013 |
Formally verifying transfer functions of analog circuits using theorem proving HT Syeda, O Hasan National University of Sciences and Technology, 2017 | 1 | 2017 |
Verified Systems Programming Made Sweeter JÅ Pohjola, HT Syeda, M Tanaka, K Winter, TW Sau, B Nott, TT Ung, ... | | 2023 |