Self-adaptive Cache Architecture Based on Run-time Hardware Counters and Offline Profiling of Applications R Cammarota, K Yalamanchili, A Ansari, AK Panda, RG Beraha US Patent App. 14/801,329, 2017 | 24 | 2017 |
Adaptive hardware reconfiguration of configurable co-processor cores for hardware optimization of functionality blocks based on use case prediction, and related methods … K Yalamanchili, YN Nagaraj, RK Iyengar, D Krishnaswamy, RG Beraha US Patent 9,286,084, 2016 | 16 | 2016 |
SHMEM+ A multilevel-PGAS programming model for reconfigurable supercomputing V Aggarwal, AD George, C Yoon, K Yalamanchili, H Lam ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (3), 1-24, 2011 | 13 | 2011 |
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+ V Aggarwal, A George, K Yalamanchili, C Yoon, H Lam, G Stitt Proceedings of the Third International Workshop on High-Performance …, 2009 | 10 | 2009 |
Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications D Majeti, A Pasalapudi, K Yalamanchili 2009 Second International Conference on Emerging Trends in Engineering …, 2009 | 8 | 2009 |
Design of optimal architectures using homogeneous routers for application specific network on chip K Yalamanchili, A Pasalapudi, D Majeti, V Sunitha 2008 First International Conference on Emerging Trends in Engineering and …, 2008 | 7 | 2008 |
Evaluation of Performance Optimal Tree Based Application Specific Network on Chip Architectures K Yalamanchili, A Pasalapudi, A Dargar, S Mehrotra, H Ved 2009 IEEE International Advance Computing Conference, 620-623, 2009 | 2 | 2009 |
Use case based reconfiguration of co-processor cores for general purpose processors K Yalamanchili US Patent 9,183,174, 2015 | | 2015 |
Evaluation of performance optimal tree based application specific network on chip A Dargar, H Ved, K Yalamanchili, PM Aditya, S Mehrotra Institute of Electrical and Electronics Engineers, 2009 | | 2009 |
Co-processor for spectral estimation of non uniformly sampled multiband signal using recursive least square based adaptive FIR filter K Yalamanchili, G Sravan, C Vijaykumar | | 2008 |
Parallel DCT computation with network on chip and analysis on mesh and star topologies S Gupta, K Yalamanchili | | 2008 |
Topology design using network simulator-2 for parallel FFT computation with network on chip K Yalamanchili, S Gupta, M Divya | | 2008 |
SHMEM+: A Multilevel-PGAS Programming Model for Reconfigurable Supercomputing VA AL, AD GEORGE, C YOON, K YALAMANCHILI, H LAM | | |
Topology design using Network Simulator (NS2) for parallel FFT computation with Network on chip DAIDAI DA-IICT | | |