Qijing Jenny Huang
Qijing Jenny Huang
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Cited by
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FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud
S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas
Y Yang, Q Huang, B Wu, T Zhang, L Ma, G Gambardella, M Blott, ...
Proceedings of the 2019 ACM/SIGDA international symposium on field …, 2019
From software to accelerators with LegUp high-level synthesis
A Canis, J Choi, B Fort, R Lian, Q Huang, N Calagar, M Gort, JJ Qin, ...
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
The effect of compiler optimizations on high-level synthesis for FPGAs
Q Huang, R Lian, A Canis, J Choi, R Xi, S Brown, J Anderson
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
Hawq-v3: Dyadic neural network quantization
Z Yao, Z Dong, Z Zheng, A Gholami, J Yu, E Tan, L Wang, Q Huang, ...
International Conference on Machine Learning, 11875-11886, 2021
Autockt: Deep reinforcement learning of analog circuit designs
K Settaluri, A Haj-Ali, Q Huang, K Hakhamaneshi, B Nikolic
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 490-495, 2020
Autophase: Juggling hls phase orderings in random forests with deep reinforcement learning
Q Huang, A Haj-Ali, W Moses, J Xiang, I Stoica, K Asanovic, J Wawrzynek
arXiv preprint arXiv:2003.00671, 2020
The effect of compiler optimizations on high-level synthesis-generated hardware
Q Huang, R Lian, A Canis, J Choi, R Xi, N Calagar, S Brown, J Anderson
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (3), 1-26, 2015
Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim
F Farshchi, Q Huang, H Yun
2019 2nd Workshop on Energy Efficient Machine Learning and Cognitive …, 2019
Fpga accelerated indel realignment in the cloud
L Wu, D Bruns-Smith, FA Nothaft, Q Huang, S Karandikar, J Le, A Lin, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
Cosa: Scheduling by constrained optimization for spatial accelerators
Q Huang, M Kang, G Dinh, T Norell, A Kalaiah, J Demmel, J Wawrzynek, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
Codenet: Efficient deployment of input-adaptive object detection on embedded fpgas
Q Huang, D Wang, Z Dong, Y Gao, Y Cai, T Li, B Wu, K Keutzer, ...
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021
Bru: Bandwidth regulation unit for real-time multicore processors
F Farshchi, Q Huang, H Yun
2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2020
Centrifuge: Evaluating full-system HLS-generated heterogeneous-accelerator SoCs using FPGA-Acceleration
Q Huang, C Yarp, S Karandikar, N Pemberton, B Brock, L Ma, G Dai, ...
Hao: Hardware-aware neural architecture optimization for efficient inference
Z Dong, Y Gao, Q Huang, J Wawrzynek, HKH So, K Keutzer
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021
Protuner: tuning programs with monte carlo tree search
A Haj-Ali, H Genc, Q Huang, W Moses, J Wawrzynek, K Asanović, I Stoica
arXiv preprint arXiv:2005.13685, 2020
Synthesis of program binaries into FPGA accelerators with runtime dependence validation
S Cheng, Q Huang, J Wawrzynek
2017 International Conference on Field Programmable Technology (ICFPT), 96-103, 2017
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Q Huang, C Hong, J Wawrzynek, M Subedar, YS Shao
2022 IEEE International Symposium on Performance Analysis of Systems and …, 2022
Autophase V2: Towards Function Level Phase Ordering Optimization
M Almakki, A Izzeldin, Q Huang, AH Ali, C Cummins
Co-design ofAlgorithms, Hardware, and Scheduling for Deep Learning Applications
Q Huang
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