| Implementation of scalable power and area efficient high-throughput Viterbi decoders T Gemmeke, M Gansen, TG Noll IEEE Journal of Solid-State Circuits 37 (7), 941-948, 2002 | 62 | 2002 |
| A parametrizable low-power high-throughput turbo-decoder G Prescher, T Gemmeke, TG Noll Proceedings.(ICASSP'05). IEEE International Conference on Acoustics, Speech …, 2005 | 50 | 2005 |
| Reliable and energy-efficient 1MHz 0.4 V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS M Konijnenburg, Y Cho, M Ashouei, T Gemmeke, C Kim, J Hulzink, J Stuyt, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 48 | 2013 |
| Design optimization of low-power high-performance DSP building blocks T Gemmeke, M Gansen, HJ Stockmanns, TG Noll IEEE Journal of Solid-State Circuits 39 (7), 1131-1139, 2004 | 34 | 2004 |
| 10.6 A 0.74 V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4 GHz Bluetooth Smart/ZigBee/IEEE 802.15. 6 personal area networks C Bachmann, GJ Van Schaik, B Busze, M Konijnenburg, Y Zhang, J Stuyt, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 25 | 2014 |
| A cortex-M3 based MCU featuring AVS with 34nW static power, 15.3 pJ/inst. active energy, and 16% power variation across process and temperature R Salvador, A Sanchez, X Fan, T Gemmeke ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 24 | 2018 |
| Method and apparatus for monitoring timing of critical paths T Gemmeke, M Konijnenburg US Patent 8,860,502, 2014 | 24 | 2014 |
| Efficiency versus accuracy: a review of design techniques for DNN hardware accelerators C Latotzke, T Gemmeke IEEE Access 9, 9785-9799, 2021 | 22 | 2021 |
| Synthesizable memory arrays based on logic gates for subthreshold operation in IoT X Fan, J Stuijt, B Liu, T Gemmeke IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 941-954, 2018 | 21 | 2018 |
| Low-cost DNN hardware accelerator for wearable, high-quality cardiac arrythmia detection J Loh, J Wen, T Gemmeke 2020 IEEE 31st International Conference on Application-specific Systems …, 2020 | 20 | 2020 |
| Method and system for verifying the equivalence of digital circuits T Gemmeke, J Leenstra, N Maeding, H Mony US Patent 7,890,901, 2011 | 19 | 2011 |
| From quantitative analysis to synthesis of efficient binary neural networks T Stadtmann, C Latotzke, T Gemmeke 2020 19th IEEE International Conference on Machine Learning and Applications …, 2020 | 16 | 2020 |
| Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing T Gemmeke, J Stuijt, MMS Aly, P Raghavan, D Atienza Alonso, F Catthoor Proceedings of the IEEE/ACM 2014 Design Automation and Test in Europe (DATE …, 2014 | 15 | 2014 |
| Permute unit and method to operate a permute unit T Gemmeke, J Leenstra, D Wendel US Patent 8,312,069, 2012 | 15 | 2012 |
| Cell libraries for robust low-voltage operation in nanometer technologies T Gemmeke, M Ashouei, B Liu, M Meixner, TG Noll, H de Groot Solid-state electronics 84, 132-141, 2013 | 14 | 2013 |
| Formally deriving a minimal clock-gating scheme H Barowski, JA Butts, T Gemmeke, N Maeding, V Paruthi US Patent 7,849,428, 2010 | 13 | 2010 |
| Review of manufacturing process defects and their effects on memristive devices LMB Poehls, MCR Fieback, S Hoffmann-Eifert, T Copetti, E Brum, ... Journal of electronic testing 37, 427-437, 2021 | 10 | 2021 |
| Classification of resilience techniques against functional errors at higher abstraction layers of digital systems G Psychou, D Rodopoulos, MM Sabry, T Gemmeke, D Atienza, TG Noll, ... ACM Computing Surveys (CSUR) 50 (4), 1-38, 2017 | 10 | 2017 |
| Variability aware cell library optimization for reliable sub-threshold operation T Gemmeke, M Ashouei 2012 Proceedings of the European Solid-State Device Research Conference …, 2012 | 10 | 2012 |
| Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip T Gemmeke, C Jaeschke, J Kuenzer, C Lichtenau, T Pflueger, J Preiss US Patent 7,996,738, 2011 | 10 | 2011 |
David AtienzaProfessor of Electrical and Computer Engineering, EPFLBestätigte E-Mail-Adresse bei epfl.ch
