An improved design of a reversible fault tolerant lut-based fpga MU Haque, ZT Sworna, HMH Babu 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 10 | 2016 |

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array ZT Sworna, M UlHaque, N Tara, HM Hasan Babu, AK Biswas IET Circuits, Devices & Systems 10 (3), 163-172, 2016 | 9 | 2016 |

A fast fpga-based bcd adder MU Haque, ZT Sworna, HMH Babu, AK Biswas Circuits, Systems, and Signal Processing 37 (10), 4384-4408, 2018 | 6 | 2018 |

A LUT-based matrix multiplication using neural networks ZT Sworna, MU Haque, HMH Babu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1982-1985, 2016 | 6 | 2016 |

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem ZT Sworna, MU Haque, HMH Babu, L Jamal, AK Biswas 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 116-121, 2017 | 4 | 2017 |

An FPGA-based divider circuit using simulated annealing algorithm ZT Sworna, MU Haque, S Rahman 2018 18th International Symposium on Communications and Information …, 2018 | 3 | 2018 |

Two Novel Design Approaches for Optimized Reversible Multiplier Circuit S Afrin, F Shihab, ZT Sworna 2019 IEEE International WIE Conference on Electrical and Computer …, 2019 | 1 | 2019 |

High-Speed and Area-Efficient LUT-Based BCD Multiplier Design ZT Sworna, MUI Haque, DM Anisuzzaman 2018 IEEE International WIE Conference on Electrical and Computer …, 2018 | 1 | 2018 |

A cost-efficient look-up table based binary coded decimal adder design ZT Sworna, MU Haque, HMH Babu, L Jamal IEEE, 874-882, 2017 | 1 | 2017 |

Efficient Design of a Reversible Sorting Circuit MA Brishty, MR Talukder, FS Shan, SA Mim, MU Haque, ZT Sworna 2019 2nd International Conference on Innovation in Engineering and …, 2019 | | 2019 |

A Fast and Compact Binary to BCD Converter Circuit N Hossain, N Hossain, ZT Sworna, MU Haque 2019 IEEE International WIE Conference on Electrical and Computer …, 2019 | | 2019 |

A Compact Quantum Cost-Efficient Design of a Reversible Binary Counter MU Haque, ZT Sworna, S Afrin, FS Shan 2019 IEEE International WIE Conference on Electrical and Computer …, 2019 | | 2019 |

ISVLSI 2017 Additional Reviewers A Srivastava, A Singh, A Ilic, A Barteau, A Dantas, B Ege, ... | | |

Efficient Design of a Reversible Sorting Circuit in Nanotechnology MA Brishty, MR Talukder, FS Shan, SA Mim, MU Haque, ZT Sworna | | |

Low Power and Area Efficient BCD Adder Design Using a LUT-Based FPGA ZT SWORNA, NT MUBIN-UL-HAQUE, HMDH BABU, AK BISWAS, ... | | |