Yuhwan Ro (노유환)
Yuhwan Ro (노유환)
Principal Researcher (Samsung Advanced Institute of Technology), Ph.D. (Seoul National University)
Bestätigte E-Mail-Adresse bei snu.ac.kr - Startseite
Titel
Zitiert von
Zitiert von
Jahr
A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth
Y Choi, I Song, MH Park, H Chung, S Chang, B Cho, J Kim, Y Oh, D Kwon, ...
2012 IEEE International Solid-State Circuits Conference, 46-48, 2012
4172012
A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput
KJ Lee, BH Cho, WY Cho, S Kang, BG Choi, HR Oh, CS Lee, HJ Kim, ...
IEEE Journal of Solid-State Circuits 43 (1), 150-162, 2008
3542008
A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput
KJ Lee, BH Cho, WY Cho, S Kang, BG Choi, HR Oh, CS Lee, HJ Kim, ...
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical …, 2007
3542007
A 0.1- 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
S Kang, WY Cho, BH Cho, KJ Lee, CS Lee, HR Oh, BG Choi, Q Wang, ...
IEEE Journal of Solid-State Circuits 42 (1), 210-218, 2006
2362006
Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations
YH Son, O Seongil, Y Ro, JW Lee, JH Ahn
Proceedings of the 40th Annual International Symposium on Computer …, 2013
1242013
Variable resistance memory device and method of manufacturing the same
Y Ro, B Choi, W Cho, H Oh
US Patent 8,116,129, 2012
1052012
A 58nm 1.8 v 1gb pram with 6.4 mb/s program bw
H Chung, BH Jeong, BJ Min, Y Choi, BH Cho, J Shin, J Kim, J Sunwoo, ...
2011 IEEE International Solid-State Circuits Conference, 500-502, 2011
1052011
Resistance variable memory devices and read methods thereof
J Bae, D Kim, K Lee, H Oh, B Cho, B Choi, WY Cho, YH Ro
US Patent 8,243,542, 2012
622012
A 0.1/spl mu/m 1.8 v 256mb 66mhz synchronous burst pram
S Kang, WY Cho, BH Cho, KJ Lee, CS Lee, HR Oh, BG Choi, Q Wang, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
392006
Phase change memory device and related programming method
YH Ro, KJ Lee, S Kang, WY Cho
US Patent 7,522,449, 2009
352009
Phase-changeable memory device and method of programming the same
H Kim, DE Kim, KJ Lee, YH Ro
US Patent 7,486,536, 2009
342009
Phase-changeable memory device and read method thereof
WY Cho, BG Choi, DE Kim, HR Oh, BH Cho, YH Ro
US Patent 7,391,644, 2008
232008
Non-volatile phase-change memory device and method of reading the same
YH Ro, WY Cho, BG Choi
US Patent 7,885,098, 2011
222011
Phase change random access memory and method of testing the same
BG Choi, BH Cho, DE Kim, C Choi, YH Ro
US Patent 7,573,766, 2009
142009
Phase change memory devices and program methods
BG Choi, DE Kim, YH Ro, JY Choi, BH Cho, WY Cho
US Patent 7,499,316, 2009
112009
Leveraging Power-performance Relationship of Energy-efficient Modern DRAM Devices
S Lee, H Cho, YH Son, Y Ro, NS Kim, JH Ahn
IEEE Access 6, 31387 - 31398, 2018
102018
Memory system including a resistance variable memory device
BG Choi, WY Cho, DE Kim, HR Oh, BH Cho, YH Ro
US Patent 7,668,007, 2010
9*2010
A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021
62021
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems
Y Ro, M Sung, Y Park, JH Ahn
IEICE Electronics Express 14 (11), 2017
52017
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture
YH Son, H Cho, Y Ro, JW Lee, JH Ahn
IEEE Computer Architecture Letters 16 (1), 76-79, 2016
52016
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