| Spatial composition grading of binary metal alloy gate electrode for short-channel SOI/SON MOSFET application B Manna, S Sarkhel, N Islam, S Sarkar, SK Sarkar IEEE Transactions on Electron Devices 59 (12), 3280-3287, 2012 | 82 | 2012 |
| Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor S Sarkhel, N Bagga, SK Sarkar Journal of Computational Electronics 15, 104-114, 2016 | 37 | 2016 |
| A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects S Sarkhel, SK Sarkar Superlattices and Microstructures 82, 293-302, 2015 | 19 | 2015 |
| 3D modelling and performance analysis of dual material tri-gate tunnel field effect transistor P Saha, S Sarkhel, SK Sarkar IETE Technical review 36 (2), 117-129, 2019 | 18 | 2019 |
| Recent research trends in gate engineered tunnel FET for improved current behavior by subduing the ambipolar effects: A review N Bagga, S Sarkhel, SK Sarkar International Conference on Computing, Communication & Automation, 1264-1267, 2015 | 15 | 2015 |
| Reduced SCEs in fully depleted dual-material double-gate (DMDG) SON MOSFET: Analytical modeling and simulation S Sarkhel, S Naha, SK Sarkar International Journal of Scientific & Engineering Research 3 (6), 1-5, 2012 | 14 | 2012 |
| Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET P Saha, S Sarkhel, SK Sarkar Journal of Computational Electronics 16, 648-657, 2017 | 13 | 2017 |
| Analytical modeling and simulation of a linearly graded binary metal alloy gate nanoscale cylindrical MOSFET for reduced short channel effects S Sarkhel, B Manna, SK Sarkar Journal of Computational Electronics 13, 599-605, 2014 | 13 | 2014 |
| A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance S Sarkhel, SK Sarkar Journal of Computational Electronics 13, 925-932, 2014 | 11 | 2014 |
| A compact analytical model of binary metal alloy silicon-on-nothing (bmason) tunnel fet with interface trapped charges S Sarkhel, N Bagga, SK Sarkar Journal of Computational Electronics 16, 704-713, 2017 | 9 | 2017 |
| 3D Modeling based Performance Analysis of Gate Engineered Trigate SON TFET with SiO2/HfO2stacked gate oxide P Saha, S Sarkhel, P Banerjee, SK Sarkar 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 8 | 2018 |
| Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance N Bagga, S Sarkhel, SK Sarkar IETE Journal of Research, 2016 | 6 | 2016 |
| Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET P Saha, S Sarkhel, SK Sarkar Journal of Electronic Materials 48, 3823-3832, 2019 | 5 | 2019 |
| A compact two dimensional analytical modeling of nanoscale fully depleted dual material gate strained SOI/SON MOSFETs for subdued SCEs S Sarkhel, B Manna, SK Sarkar Journal of Low Power Electronics 10 (3), 383-391, 2014 | 5 | 2014 |
| Device circuit co-design of FD-SON MOSFET model using BSIMSOI MOSFET model D Saha, K Naskar, S Sarkhel, B Manna, SK Sarkar IEEE CONECCT, 2013 | 5 | 2013 |
| Exploring the threshold voltage characteristics and short channel behavior of gate engineered front gate stack MOSFET with graded channel S Sarkhel, P Saha, SK Sarkar Silicon 11 (3), 1421-1428, 2019 | 4 | 2019 |
| Analytical modeling and performance characterization of a double gate MOSFET with dielectric pockets incorporating work function engineered binary metal alloy gate electrode … R Saha, S Sarkhel, SK Sarkar IETE Technical Review 35 (5), 506-513, 2018 | 3 | 2018 |
| A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient K Mukherjee, T Sau, S Upadhyay, S Mitra, A Bhowmik, S Sarkhel, ... International Journal of Numerical Modelling: Electronic Networks, Devices …, 2022 | 2 | 2022 |
| A 0.6 V 1.6 nA Constant Current Reference Circuit with Improved Power Supply Sensitivity T Saquib, S Sarkhel, S Pandit 2021 Devices for Integrated Circuit (DevIC), 498-503, 2021 | 2 | 2021 |
| Comparative study of doublet ota circuit topologies operating in weak inversion mode for low power analog ic applications R Aditya, S Sarkel, S Pandit 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 74-78, 2020 | 2 | 2020 |
Navjeet BaggaAssistant Professor@ IIT BhubaneswarBestätigte E-Mail-Adresse bei iitbbs.ac.in
