| Caracterização elétrica de tecnologia e dispositivos MOS PB Verdonck Cengage Learning Editores, 2004 | 158 | 2004 |
| Analog performance and application of graded-channel fully depleted SOI MOSFETs MA Pavanello, JA Martino, V Dessard, D Flandre Solid-State Electronics 44 (7), 1219-1222, 2000 | 128 | 2000 |
| Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects MA Pavanello, JA Martino, D Flandre Solid-State Electronics 44 (6), 917-922, 2000 | 114 | 2000 |
| BJT effect analysis in p-and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application M Galeti, M Rodrigues, JA Martino, N Collaert, E Simoen, M Aoulaiche, ... IEEE 2011 International SOI Conference, 1-2, 2011 | 93 | 2011 |
| Temperature impact on the tunnel fet off-state current components PG Der Agopian, MDV Martino, SG dos Santos Filho, JA Martino, ... Solid-state electronics 78, 141-146, 2012 | 88 | 2012 |
| Experimental comparison between trigate p-TFET and p-FinFET analog performance as a function of temperature PG Der Agopian, JA Martino, R Rooyackers, A Vandooren, E Simoen, ... IEEE Transactions on Electron Devices 60 (8), 2493-2497, 2013 | 79 | 2013 |
| An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics MA Pavanello, JA Martino, V Dessard, D Flandre Electrochemical and Solid-State Letters 3 (1), 50, 1999 | 78 | 1999 |
| Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source FS Neves, PGD Agopian, JA Martino, B Cretu, R Rooyackers, ... IEEE Transactions on Electron Devices 63 (4), 1658-1665, 2016 | 72 | 2016 |
| InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature A Alian, Y Mols, CCM Bordallo, D Verreck, A Verhulst, A Vandooren, ... Applied Physics Letters 109 (24), 2016 | 67 | 2016 |
| Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor A Cerdeira, MA Alemán, MA Pavanello, JA Martino, L Vancaillie, ... IEEE Transactions on Electron Devices 52 (5), 967-972, 2005 | 64 | 2005 |
| Analog circuit design using graded-channel silicon-on-insulator nMOSFETs MA Pavanello, JA Martino, D Flandre Solid-State Electronics 46 (8), 1215-1225, 2002 | 54 | 2002 |
| Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation MA Pavanello, JA Martino, E Simoen, R Rooyackers, N Collaert, C Claeys Solid-State Electronics 51 (2), 285-291, 2007 | 49 | 2007 |
| The dependence of retention time on gate length in UTBOX FBRAM with different source/drain junction engineering T Nicoletti, M Aoulaiche, LM Almeida, SD Santos, JA Martino, A Veloso, ... IEEE electron device letters 33 (7), 940-942, 2012 | 42 | 2012 |
| Behavior of triple-gate Bulk FinFETs with and without DTMOS operation MGC de Andrade, JA Martino, M Aoulaiche, N Collaert, E Simoen, ... Solid-state electronics 71, 63-68, 2012 | 42 | 2012 |
| Influence of the source composition on the analog performance parameters of vertical nanowire-TFETs PGD Agopian, MDV Martino, SD dos Santos, FS Neves, JA Martino, ... IEEE Transactions on Electron Devices 62 (1), 16-22, 2014 | 40 | 2014 |
| Threshold voltage extraction in Tunnel FETs A Ortiz-Conde, FJ García-Sánchez, J Muci, A Sucre-González, JA Martino, ... Solid-State Electronics 93, 49-55, 2014 | 39 | 2014 |
| Modeling silicon on insulator MOS transistors with nonrectangular-gate layouts R Giacomini, JA Martino Journal of the Electrochemical Society 153 (3), G218, 2006 | 39 | 2006 |
| Study of line-TFET analog performance comparing with other TFET and MOSFET architectures PG Der Agopian, JA Martino, A Vandooren, R Rooyackers, E Simoen, ... Solid-State Electronics 128, 43-47, 2017 | 38 | 2017 |
| Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects R Giacomini, JA Martino Journal of the Electrochemical Society 155 (4), H213, 2008 | 38 | 2008 |
| Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics SD Dos Santos, B Cretu, V Strobel, JM Routoure, R Carin, JA Martino, ... Solid-state electronics 97, 14-22, 2014 | 36 | 2014 |
C. ClaeysProfessor KU LeuvenBestätigte E-Mail-Adresse bei kuleuven.be
