Mark Stephenson
Mark Stephenson
NVIDIA Research
Bestätigte E-Mail-Adresse bei - Startseite
Zitiert von
Zitiert von
Meta optimization: Improving compiler heuristics with machine learning
M Stephenson, S Amarasinghe, M Martin, UM O'Reilly
ACM sigplan notices 38 (5), 77-90, 2003
Bidwidth analysis with application to silicon compilation
M Stephenson, J Babb, S Amarasinghe
ACM SIGPLAN Notices 35 (5), 108-120, 2000
Predicting unroll factors using supervised classification
M Stephenson, S Amarasinghe
International symposium on code generation and optimization, 123-134, 2005
Page placement strategies for GPUs within heterogeneous memory systems
N Agarwal, D Nellans, M Stephenson, M O'Connor, SW Keckler
Proceedings of the Twentieth International Conference on Architectural …, 2015
Flexible Software Profiling of GPU Architectures
M Stephenson, SKS Hari, Y Lee, E Ebrahimi, DR Johnson, D Nellans, ...
International Symposium on Computer Architecture (ISCA), 2015
Towards high performance paged memory for GPUs
T Zheng, D Nellans, A Zulfiqar, M Stephenson, SW Keckler
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
Sassifi: An architecture-level fault injection tool for gpu application resilience evaluation
SKS Hari, T Tsai, M Stephenson, SW Keckler, J Emer
2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017
Genetic programming applied to compiler heuristic optimization
M Stephenson, UM O’Reilly, MC Martin, S Amarasinghe
European conference on genetic programming, 238-253, 2003
SASSIFI: Evaluating Resilience of GPU Applications
SKS Hari, T Tsai, M Stephenson, S Keckler, J Emer
The 11th Workshop on Silicon Errors in Logic - System Effects, 2015
Nvbit: A dynamic binary instrumentation framework for nvidia gpus
O Villa, M Stephenson, D Nellans, SW Keckler
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Exploring the design space of SPMD divergence management on data-parallel architectures
Y Lee, V Grover, R Krashinsky, M Stephenson, SW Keckler, K Asanovic
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 101-113, 2014
Bitwise: Optimizing bitwidths using data-range propagation
MW Stephenson
Massachusetts Institute of Technology, 2000
Automating the construction of a complier heuristics using machine learning
MW Stephenson
Massachusetts Institute of Technology, 2006
The power 775 architecture at scale
R Rajamony, MW Stephenson, WE Speight
Proceedings of the 27th international ACM conference on International …, 2013
Using hardware interrupts to drive dynamic binary code recompilation
MW Stephenson, R Rangan
US Patent 8,453,129, 2013
Predication supporting code generation by indicating path associations of symmetrically placed write instructions
R Rangan, MW Stephenson, L Zhang
US Patent 9,262,140, 2016
Automatically exploiting implicit pipeline parallelism from multiple dependent kernels for gpus
G Kim, J Jeong, J Kim, M Stephenson
Proceedings of the 2016 International Conference on Parallel Architectures …, 2016
Adapting convergent scheduling using machine-learning
D Puppin, M Stephenson, S Amarasinghe, M Martin, UM O’Reilly
International Workshop on Languages and Compilers for Parallel Computing, 17-31, 2003
Energy-efficient failure detection and masking
EN Elnozahy, MW Stephenson
US Patent 8,448,027, 2013
Variable-depth audio presentation of textual information
PJ Bohrer, MD Kistler, R Rajamony, MW Stephenson
US Patent 9,431,004, 2016
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