Folgen
Bertrand Parvais
Bertrand Parvais
imec & VUB
Bestätigte E-Mail-Adresse bei imec.be
Titel
Zitiert von
Zitiert von
Jahr
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
LÅ Ragnarsson, Z Li, J Tseng, T Schram, E Rohr, MJ Cho, T Kauerauf, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
3012009
Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective
V Subramanian, B Parvais, J Borremans, A Mercha, D Linten, P Wambacq, ...
IEEE Transactions on Electron Devices 53 (12), 3071-3079, 2006
1892006
3D stacked IC demonstration using a through silicon via first approach
J Van Olmen, A Mercha, G Katti, C Huyghebaert, J Van Aelst, E Seppala, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
1822008
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
T Chiarella, L Witters, A Mercha, C Kerner, M Rakowski, C Ortolland, ...
Solid-State Electronics 54 (9), 855-860, 2010
1592010
Impact of fin width on digital and analog performances of n-FinFETs
V Subramanian, A Mercha, B Parvais, J Loo, C Gustin, M Dehan, ...
Solid-State Electronics 51 (4), 551-559, 2007
1142007
Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
D Flandre, S Adriaensen, A Akheyar, A Crahay, L Demeûs, P Delatte, ...
Solid-State Electronics 45 (4), 541-549, 2001
1132001
A low-power 57-to-66GHz transceiver in 40nm LP CMOS with− 17dB EVM at 7Gb/s
V Vidojkovic, G Mangraviti, K Khalaf, V Szortyka, K Vaesen, W Van Thillo, ...
2012 IEEE International Solid-State Circuits Conference, 268-270, 2012
1012012
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
982017
A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication
V Vidojkovic, V Szortyka, K Khalaf, G Mangraviti, S Brebels, W Van Thillo, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
872013
Double-gate FinFETs as a CMOS technology downscaling option: An RF perspective
S Nuttinck, B Parvais, G Curatola, A Mercha
IEEE Transactions on electron Devices 54 (2), 279-283, 2007
862007
Dependence of FinFET RF performance on fin width
D Lederer, B Parvais, A Mercha, N Collaert, M Jurczak, JP Raskin, ...
Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated …, 2006
782006
MoM simulation of signal-to-noise patterns in infinite and finite receiving antenna arrays
C Craeye, B Parvais, X Dardenne
IEEE Transactions on Antennas and Propagation 52 (12), 3245-3256, 2004
702004
Physical model of low-temperature to cryogenic threshold voltage in MOSFETs
A Beckers, F Jazaeri, A Grill, S Narasimhamoorthy, B Parvais, C Enz
IEEE Journal of the Electron Devices Society 8, 780-788, 2020
692020
Scalable and multibias high frequency modeling of multi-fin FETs
G Crupi, D Schreurs, B Parvais, A Caddemi, A Mercha, S Decoutere
Solid-state electronics 50 (11-12), 1780-1786, 2006
632006
CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance
U Peralagu, A Alian, V Putcha, A Khaled, R Rodriguez, ...
2019 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2019
622019
A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
B Kaczer, J Franco, P Weckx, PJ Roussel, V Putcha, E Bury, M Simicic, ...
Microelectronics Reliability 81, 186-194, 2018
602018
21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS
V Szortyka, Q Shi, K Raczkowski, B Parvais, M Kuijk, P Wambacq
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
602014
A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS
V Szortyka, Q Shi, K Raczkowski, B Parvais, M Kuijk, P Wambacq
IEEE Journal of Solid-State Circuits 50 (9), 2025-2036, 2015
592015
The potential of FinFETs for analog and RF circuit applications
P Wambacq, B Verbruggen, K Scheir, J Borremans, M Dehan, D Linten, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2541-2551, 2007
592007
Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs
V Subramaniana, B Parvais, J Borremans, A Mercha, D Linten, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
592005
Das System kann den Vorgang jetzt nicht ausführen. Versuchen Sie es später erneut.
Artikel 1–20