A 6-Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os T Oh, R Harjani
IEEE Journal of Solid-State Circuits 46 (8), 1843-1856, 2011
47 2011 A 12-Gb/s multichannel I/O using MIMO crosstalk cancellation and signal reutilization in 65-nm CMOS T Oh, R Harjani
IEEE journal of solid-state circuits 48 (6), 1383-1397, 2013
46 2013 A 5Gb/s 2× 2 MIMO crosstalk cancellation scheme for high-speed I/Os T Oh, R Harjani
IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010
15 2010 IEEE JSSC HR Oh, D Ward, R Dutton
SC-15, 636-643, 1980
12 1980 4× 12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS T Oh, R Harjani
2012 symposium on VLSI circuits (VLSIC), 140-141, 2012
9 2012 Adaptive Techniques for Joint Optimization of XTC and DFE Loop Gain in High‐Speed I/O T Oh, R Harjani
ETRI Journal 37 (5), 906-916, 2015
7 2015 0.5–4.4 Gbit/s PAM4/NRZ dual‐mode transceiver with 0.6 V near‐ground NMOS driver for low‐power memory interface K Min, T Oh
Electronics Letters 54 (11), 684-685, 2018
3 2018 Single‐ended 2 ch.× 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process E Kim, T Oh
Electronics Letters 53 (5), 308-310, 2017
2 2017 Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS S Lee, R Harjani, T Oh
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (4), 2096-2100, 2022
1 2022 12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme K Park, T Oh
Electronics Letters 55 (20), 1078-1080, 2019
1 2019 2× 3.2 Gb/s single‐ended IO transmitter with low‐power dynamic FIR driver for the LPDDR4 standard S Kim, T Oh
Electronics Letters 53 (24), 1566-1568, 2017
1 2017 A 4.1 mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process E Kim, D Jeong, T Oh
2016 International SoC Design Conference (ISOCC), 75-76, 2016
1 2016 High performance multi-channel high-speed I/O circuits T Oh, R Harjani
Springer New York, 2014
1 2014 Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL T Oh, J Gil, R Harjani
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2), 264-268, 2021
2021 High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process K Min, S Lee, T Oh
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 21 (3), 199-205, 2021
2021 12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process S Lee, T Oh
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 21 (2), 152-156, 2021
2021 A 2–8-GHz adaptive duty-cycle corrector loop with background calibration E Kim, Y Lee, T Oh
International Journal of Electronics 104 (9), 1578-1588, 2017
2017 A 4Gb/s, 370µA low-power Tx FIR driver for LPDDR4 applications T Oh, MC Park, YS Eo
IEICE Electronics Express 11 (5), 20130825-20130825, 2014
2014 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS ProcessT Oh, R Harjani, T Oh, R Harjani
High Performance Multi-Channel High-Speed I/O Circuits, 11-25, 2014
2014 Research Summary and Contributions T Oh, R Harjani, T Oh, R Harjani
High Performance Multi-Channel High-Speed I/O Circuits, 69-71, 2014
2014