| Forecasting the behavior of multivariate time series using neural networks K Chakraborty, K Mehrotra, CK Mohan, S Ranka Neural networks 5 (6), 961-970, 1992 | 746 | 1992 |
| Integrated circuit architecture for reducing interconnect parasitics K Chakraborty, B Xu, X Zhou US Patent App. 11/341,747, 2007 | 244 | 2007 |
| Fault-tolerance and reliability techniques for high-density random-access memories K Chakraborty, P Mazumder Prentice Hall PTR, 2002 | 106 | 2002 |
| Testing and testable design of high-density random-access memories P Mazumder, K Chakraborty Kluwer Academic Publishers, 1996 | 77 | 1996 |
| Transformational placement and synthesis W Donath, P Kudva, L Stok, L Reddy, A Sullivan, K Chakraborty, ... Proceedings of the conference on Design, automation and test in Europe, 194-201, 2000 | 63 | 2000 |
| Connectionist models for part-family classifications K Chakraborty, U Roy Computers & Industrial Engineering 24 (2), 189-198, 1993 | 38 | 1993 |
| A physical design tool for built-in self-repairable RAMs K Chakraborty, S Kulkami, M Bhattacharya, P Mazumder, A Gupta IEEE transactions on very large scale integration (VLSI) systems 9 (2), 352-364, 2001 | 28 | 2001 |
| BISRAMGEN: A silicon compiler for built-in self-repairable random-access memories K Chakraborty University of Michigan, 1997 | 21 | 1997 |
| Method and apparatus for applying fine-grained transforms during placement synthesis interaction K Chakraborty, WE Donath, PN Kudva, LN Reddy, L Stok, AJ Sullivan, ... US Patent 7,047,163, 2006 | 17 | 2006 |
| An optimization network for solving a set of simultaneous linear equations K Chakraborty, K Mehrotta, CK Mohan, S Ranka [Proceedings 1992] IJCNN International Joint Conference on Neural Networks 2 …, 1992 | 17 | 1992 |
| A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation M Mukherjee, K Chakraborty Information processing letters 83 (1), 41-48, 2002 | 15 | 2002 |
| Fine-grained power management of synchronous and asynchronous datapath circuits K Chakraborty, SE Strauss, B Xu US Patent 7,511,535, 2009 | 12 | 2009 |
| System and method for suppressing crosstalk glitch in digital circuits K Chakraborty, TJ Gabara, KR Stiles, B Xu US Patent 7,409,659, 2008 | 12 | 2008 |
| A randomized greedy method for rectangular-pattern fill problems M Mukherjee, K Chakraborty IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 9 | 2008 |
| Method of configuring integrated circuits using greedy algorithm for partitioning of N points in P isothetic rectangles K Chakraborty, M Mukherjee US Patent 6,532,578, 2003 | 9 | 2003 |
| Testing and reliability techniques for high-bandwidth embedded RAMs K Chakraborty Journal of Electronic Testing 20 (1), 89-108, 2004 | 7 | 2004 |
| Embedded memory testing using back-to-back write/read operations K Chakraborty, N Purushotham US Patent 9,728,273, 2017 | 6 | 2017 |
| A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs K Chakraborty, P Mazumder Proceedings European Design and Test Conference. ED & TC 97, 330-334, 1997 | 6 | 1997 |
| Technology and layout-related testing of static random-access memories K Chakraborty, P Mazumder Journal of Electronic Testing 5, 347-365, 1994 | 6 | 1994 |
| Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing N Purushotham, K Chakraborty, D Ratchen US Patent App. 14/482,001, 2015 | 5 | 2015 |
Sanjay RankaUniversity of FloridaVerified email at cise.ufl.edu
