Anders Landin
Anders Landin
Cerebras systems
Bestätigte E-Mail-Adresse bei
Zitiert von
Zitiert von
DDM-a cache-only memory architecture
E Hagersten, A Landin, S Haridi
Computer 25 (9), 44-54, 1992
Queue locks on cache coherent multiprocessors
P Magnusson, A Landin, E Hagersten
Proceedings of 8th International Parallel Processing Symposium, 165-171, 1994
Rock: A high-performance sparc cmt processor
S Chaudhry, R Cypher, M Ekman, M Karlsson, A Landin, S Yip, H Zeffer, ...
IEEE micro 29 (2), 6-16, 2009
An argument for simple COMA
A Saulsbury, T Wilkinson, J Carter, A Landin
Future Generation Computer Systems 11 (6), 553-566, 1995
Optical interconnects: out of the box forever?
D Huang, T Sze, A Landin, R Lytel, HL Davidson
IEEE Journal of Selected Topics in Quantum Electronics 9 (2), 614-623, 2003
Race-free interconnection networks and multiprocessor consistency
A Landin, E Hagersten, S Haridi
Proceedings of the 18th Annual International Symposium on Computer …, 1991
Simultaneous speculative threading: A novel pipeline architecture implemented in sun's rock processor
S Chaudhry, R Cypher, M Ekman, M Karlsson, A Landin, S Yip, H Zeffer, ...
ACM SIGARCH Computer Architecture News 37 (3), 484-495, 2009
Apparatus and method for memory address translation across multiple nodes
CA Vick, A Landin, O Manczak, MH Paleczny, GM Wright
US Patent App. 11/864,851, 2009
Method and apparatus for implementing virtual transactional memory using cache line marking
RE Cypher, S Chaudhry, A Landin
US Patent 7,676,636, 2010
Performing virtual to global address translation in processing subsystem
A Landin, EE Hagersten
US Patent 7,363,462, 2008
Simple COMA node implementations
E Hagersten, A Saulsbury, A Landin
1994 Proceedings of the Twenty-Seventh Hawaii International Conference on …, 1994
Proximity communication package for processor, cache and memory
JE Cunningham, AV Krishnamoorthy, A Landin
US Patent 8,102,663, 2012
Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes
A Landin, EE Hagersten
US Patent 7,765,381, 2010
Cache hierarchy with bounds on levels accessed
R Cypher, H Zeffer, A Landin
US Patent 8,606,997, 2013
Multi-node computer system including a mechanism to encode node ID of a transaction-initiating node in invalidating proxy address packets
A Landin
US Patent App. 10/821,413, 2005
Efficient software synchronization on large cache coherent multiprocessors
PS Magnusson, A Landin, E Hagersten
SICS Research Report, 1994
DRAM remote access cache in local memory in a distributed shared memory system
HE Zeffer, A Landin, EE Hagersten
US Patent 7,509,460, 2009
Read/Write Permission Bit Support for Efficient Hardware to Software Handover
H Zeffer, E Hagersten, A Landin, K Moore
US Patent App. 11/859,955, 2008
Multi-node computer system implementing memory-correctable speculative proxy transactions
R Cypher, A Landin
US Patent App. 10/821,350, 2005
Bus-based COMA-reducing traffic in shared-bus multiprocessors
A Landin, F Dahlgren
Proceedings. Second International Symposium on High-Performance Computer …, 1996
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