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Thomas Shiple
Thomas Shiple
MIT, UC Berkeley, Synopsys
Verified email at alum.mit.edu
Title
Cited by
Cited by
Year
Constructive Analysis of Cyclic Circuits
TR Shiple, G Berry, H Touati
Proceedings European Design and Test Conference, 328-333, 1996
2141996
Smart simulation using collaborative formal and simulation engines
PH Ho, T Shiple, K Harer, J Kukula, R Damiano, V Bertacco, J Taylor, ...
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
1752000
Heuristic minimization of BDDs using don't cares
TR Shiple, R Hojati, AL Sangiovanni-Vincentelli, RK Brayton
Proceedings of the 31st annual Design Automation Conference, 225-231, 1994
1471994
HSIS: A BDD-based environment for formal verification
A Aziz, F Balarin, ST Cheng, R Hojati, T Kam, SC Krishnan, RK Ranjan, ...
Proceedings of the 31st annual Design Automation Conference, 454-459, 1994
1071994
Approximation and decomposition of binary decision diagrams
K Ravi, KL McMillan, TR Shiple, F Somenzi
Proceedings of the 35th annual Design Automation Conference, 445-450, 1998
104*1998
Formal analysis of synchronous circuits
TR Shiple
University of California, Berkeley, 1996
821996
A Comparison of Presburger Engines for EFSM Reachability
TR Shiple, JH Kukula, RK Ranjan
International Conference on Computer Aided Verification, 280-292, 1998
811998
Building circuits from relations
JH Kukula, TR Shiple
Computer Aided Verification: 12th International Conference, CAV 2000 …, 2000
662000
Formula-dependent equivalence for compositional CTL model checking
A Aziz, TR Shiple, V Singhal, AL Sangiovanni-Vincentelli
Computer Aided Verification: 6th International Conference, CAV'94 Stanford …, 1994
571994
Constructive Boolean circuits and the exactness of timed ternary simulation
M Mendler, TR Shiple, G Berry
Formal Methods in System Design 40, 283-329, 2012
492012
VIS
RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ...
International Conference on Formal Methods in Computer-Aided Design, 248-256, 1996
491996
Analysis of combinational cycles in sequential circuits
TR Shiple, V Singhal, RK Brayton, AL Sangiovnni-Vincentelli
1996 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 592-595, 1996
341996
A unified approach to language containment and fair CTL model checking
R Hojati, TR Shiple, RK Brayton, RP Kurshan
Proceedings of the 30th international Design Automation Conference, 475-481, 1993
301993
Automatic compositional minimization in CTL model checking
M Chiodo, TR Shiple, AL Sangiovanni-Vincentelli, RK Brayton
IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 172-172, 1992
301992
VIS User’s Manual
T Villa, G Swamy, T Shiple, A Aziz, R Brayton, S Edwards, G Hachtel, ...
Electronics Research Laboratory, University of Colorado at Boulder, 1996
241996
Simplifying circuits for formal verification using parametric representation
IH Moon, HH Kwak, J Kukula, T Shiple, C Pixley
Formal Methods in Computer-Aided Design: 4th International Conference, FMCAD …, 2002
222002
Formula-dependent equivalence for compositional CTL model checking
A Aziz, T Shiple, V Singhal, R Brayton, A Sangiovanni-Vincentelli
Formal Methods in System Design 21, 193-224, 2002
212002
Method and system for automata-based approach to state reachability of interacting extended finite state machines
JH Kukula, TR Shiple
US Patent 6,059,837, 2000
202000
Combinational equivalence checking through function transformation
HH Kwak, IH Moon, JH Kukula, TR Shiple
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
132002
Method and apparatus for formally constraining random simulation
JH Kukula, TR Shiple, RK Ranjan
US Patent 7,092,858, 2006
82006
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