| Hardware/software co-compilation with the Nymble system J Huthmann, B Liebig, J Oppermann, A Koch 2013 8th International workshop on reconfigurable and communication-centric …, 2013 | 41 | 2013 |
| Automatic high-level synthesis of multi-threaded hardware accelerators J Huthmann, J Oppermann, A Koch 2014 24th International Conference on Field Programmable Logic and …, 2014 | 15 | 2014 |
| Precore-A token-based speculation architecture for high-level language to hardware compilation B Thielmann, J Huthmann, A Koch 2011 21st International Conference on Field Programmable Logic and …, 2011 | 13 | 2011 |
| OpenMP device offloading to FPGAs using the Nymble infrastructure J Huthmann, L Sommer, A Podobas, A Koch, K Sano OpenMP: Portable Multi-Level Parallelism on Modern Systems: 16th …, 2020 | 9 | 2020 |
| Accelerating high-level engineering computations by automatic compilation of geometric algebra to hardware accelerators J Huthmann, P Müller, F Stock, D Hildenbrand, A Koch 2010 International Conference on Embedded Computer Systems: Architectures …, 2010 | 9 | 2010 |
| Evaluation of speculative execution techniques for high-level language to hardware compilation B Thielmann, J Huthmann, A Koch 6th international workshop on reconfigurable communication-centric systems …, 2011 | 8 | 2011 |
| Scaling Performance for N-Body Stream Computation with a Ring of FPGAs J Huthmann, A Shin, A Podobas, K Sano, H Takizawa Proceedings of the 10th International Symposium on Highly-Efficient …, 2019 | 7 | 2019 |
| Architecture exploration of high-performance floating-point fused multiply-add units and their automatic use in high-level synthesis B Liebig, J Huthmann, A Koch 2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013 | 7 | 2013 |
| High-performance custom computing with FPGA cluster as an off-loading engine T Miyajima, T Ueno, A Koshiba, J Huthmann, K Sano, M Sato ACM/IEEE International Conference for High Performance Computing, Networking …, 2018 | 6 | 2018 |
| Compiling geometric algebra computations into reconfigurable hardware accelerators J Huthmann, P Müller, F Stock, D Hildenbrand, A Koch Schloss-Dagstuhl-Leibniz Zentrum für Informatik, 2010 | 5 | 2010 |
| Minimal-precision computing for high-performance, energy-efficient, and reliable computations D Mukunoki, I Toshiyuki, Y Tan, A Koshiba, J Huthmann, K Sano, ... France-Japan-Germany trilateral workshop: Convergence of HPC and Data …, 2019 | 4 | 2019 |
| Optimized high-level synthesis of SMT multi-threaded hardware accelerators J Huthmann, A Koch 2015 International Conference on Field Programmable Technology (FPT), 176-183, 2015 | 4 | 2015 |
| Memory latency hiding by load value speculation for reconfigurable computers B Thielmann, J Huthmann, A Koch ACM Transactions on Reconfigurable Technology and Systems (TRETS) 5 (3), 1-14, 2012 | 4 | 2012 |
| RAP: More efficient memory access in highly speculative execution on reconfigurable adaptive computers B Thielmann, T Wink, J Huthmann, A Koch 2011 International Conference on Reconfigurable Computing and FPGAs, 434-441, 2011 | 3 | 2011 |
| White Paper from Workshop on Large-scale Parallel Numerical Computing Technology (LSPANC 2020): HPC and Computer Arithmetic toward Minimal-Precision Computing R Iakymchuk, D Mukunoki, A Podobas, F Jézéquel, T Imamura, N Fujita, ... arXiv preprint arXiv:2004.04628, 2020 | 1 | 2020 |
| Optimizing Precision for High-Performance, Robust, and Energy-Efficient Computations R Iakymchuk, S Graillat, F Jézéquel, D Mukunoki, T Imamura, Y Tan, ... International Conference on High Performance Computing in Asia-Pacific Region,, 2020 | 1 | 2020 |
| An Execution Model and High-Level-Synthesis System for Generating SIMT Multi-Threaded Hardware from C Source Code JC Huthmann Technische Universität, 2017 | 1 | 2017 |
| Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms B Thielmann, J Huthmann, T Wink, A Koch Embedded Systems Design with FPGAs, 1-29, 2013 | 1 | 2013 |
| Neural network hardware accelerator data parallelism N Nez, O Khavin, T Ahmed, J Huthmann, S Dasgupta US Patent App. 18/299,717, 2023 | | 2023 |
| Neural network hardware accelerator data parallelism N Nez, O Khavin, T Ahmed, J Huthmann, S Dasgupta US Patent 11,657,260, 2023 | | 2023 |
Artur PodobasAssociate Professor at KTH, Royal Institute of TechnologyVerified email at podobas.net
