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Samuel H. Duncan
Samuel H. Duncan
Zugehörigkeit unbekannt
Bestätigte E-Mail-Adresse bei nvidia.com
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Zitiert von
Zitiert von
Jahr
Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
SH Duncan, CD Keefer, TA McLaughlin, PM Guglielmi
US Patent 5,953,538, 1999
1381999
Method and apparatus for providing peer-to-peer data transfer within a computing environment
SH Duncan, WJ Huang, JH Edmondson
US Patent 7,275,123, 2007
792007
Scalable efficient I/O port protocol
RE Kessler, SH Duncan, DW Hartwell, DAJ Webb Jr, S Lang
US Patent 6,738,836, 2004
772004
Method and apparatus for providing peer-to-peer data transfer within a computing environment
SH Duncan, WJ Huang, JH Edmondson
US Patent 7,451,259, 2008
582008
Read completion data management
RHM Wong, SH Duncan, L Muliadi, MV Swarna
US Patent 8,656,117, 2014
522014
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write
SH Duncan, GA Herdeg, RC Hetherington, CD Keefer, MB Steinman, ...
US Patent 6,353,877, 2002
472002
Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges
SH Duncan, CD Keefer, TA McLaughlin, PM Guglielmi
US Patent 6,012,120, 2000
432000
Anti-starvation interrupt protocol
DW Hartwell, SH Duncan, DT Mayo, DJ Golden
US Patent 6,920,516, 2005
422005
Coherent translation look-aside buffer
SH Duncan
US Patent 6,633,967, 2003
412003
Method for communicating interrupt data structure in a multi-processor computer system
GA Herdeg, SH Duncan, DT Mayo, DF Hayes
US Patent 6,021,456, 2000
402000
Block data mover adapted to contain faults in a partitioned multiprocessor system
SH Duncan, FC Canter, DD Donaldson, DW Hartwell
US Patent 6,826,653, 2004
392004
Replaying memory transactions while resolving memory access faults
JL Deming, JF Duluk Jr, J Mashey, M Hairgrove, L Dunning, JSR Evans, ...
US Patent 9,575,892, 2017
332017
System and method for error detection and reducing simultaneous switching noise
PC Wade, SH Duncan, DW Smelser
US Patent 5,481,555, 1996
331996
System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system
SH Duncan, S Ho
US Patent 6,647,453, 2003
292003
Scalable efficient I/O port protocol
RE Kessler, SH Duncan, DW Hartwell, DAJ Webb Jr, S Lang
US Patent 8,364,851, 2013
282013
IO speed and length programmable with bus population
SH Duncan, D Hayes
US Patent 6,782,438, 2004
282004
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
SH Duncan, GA Herdeg, RC Hetherington, CD Keefer, MB Steinman, ...
US Patent 6,128,711, 2000
272000
Ducati: High-performance address translation by extending tlb reach of gpu-accelerated systems
A Jaleel, E Ebrahimi, S Duncan
ACM Transactions on Architecture and Code Optimization (TACO) 16 (1), 1-24, 2019
212019
Interface that permits data bus signals to pass between high frequency processing unit and low frequency expansion devices
CE Brench, SR Coe, SH Duncan, SE Lindquist, RE Olson
US Patent 5,822,195, 1998
211998
Deadlock avoidance by marking CPU traffic as special
SH Duncan, DB Glasco, WJ Huang, A Kalambur, PR Marchand, DK Ma
US Patent 8,392,667, 2013
192013
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