Built-in redundancy analysis for memory yield improvement CT Huang, CF Wu, JF Li, CW Wu IEEE transactions on Reliability 52 (4), 386-399, 2003 | 244 | 2003 |
A built-in self-repair design for RAMs with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 742-745, 2005 | 134 | 2005 |
March-based RAM diagnosis algorithms for stuck-at and coupling faults JF Li, KL Cheng, CT Huang, CW Wu Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 758-767, 2001 | 92 | 2001 |
A built-in self-repair scheme for semiconductor memories with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu, PY Tsai, A Hsu, E Chow International Test Conference, 2003. Proceedings. ITC 2003., 393-393, 2003 | 91 | 2003 |
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs YJ Huang, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu 29th VLSI test symposium, 20-25, 2011 | 90 | 2011 |
A built-in self-test and self-diagnosis scheme for embedded SRAM CW Wang, CF Wu, JF Li, CW Wu, T Teng, K Chiu, HP Lin Proceedings of the Ninth Asian Test Symposium, 45-50, 2000 | 80 | 2000 |
Fault modeling and testing of 1T1R memristor memories YX Chen, JF Li 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015 | 76 | 2015 |
ReBISR: A reconfigurable built-in self-repair scheme for random access memories in SOCs TW Tseng, JF Li, CC Hsu IEEE transactions on very large scale integration (vlsi) systems 18 (6), 921-932, 2009 | 72 | 2009 |
ProTaR: An infrastructure IP for repairing RAMs in system-on-chips CD Huang, JF Li, TW Tseng IEEE transactions on very large scale integration (VLSI) systems 15 (10 …, 2007 | 60 | 2007 |
A simulator for evaluating redundancy analysis algorithms of repairable embedded memories RF Huang, JF Li, JC Yeh, CW Wu Proceedings of the 2002 IEEE International Workshop on Memory Technology …, 2002 | 60 | 2002 |
Built-in self-repair scheme for the TSVs in 3-D ICs YJ Huang, JF Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 59 | 2012 |
A low-power ternary content addressable memory with Pai-Sigma matchlines SH Yang, YJ Huang, JF Li IEEE transactions on very large scale integration (VLSI) systems 20 (10 …, 2011 | 46 | 2011 |
A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs TW Tseng, JF Li, CC Hsu, A Pao, K Chiu, E Chen 2006 IEEE International Test Conference, 1-9, 2006 | 46 | 2006 |
Memory fault diagnosis by syndrome compression JF Li, CW Wu Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 45 | 2001 |
Yield-enhancement techniques for 3D random access memories CW Chou, YJ Huang, JF Li Proceedings of 2010 International Symposium on VLSI Design, Automation and …, 2010 | 42 | 2010 |
A shared parallel built-in self-repair scheme for random access memories in SOCs TW Tseng, JF Li 2008 IEEE International Test Conference, 1-9, 2008 | 39 | 2008 |
A test integration methodology for 3D integrated circuits CW Chou, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu 2010 19th IEEE Asian Test Symposium, 377-382, 2010 | 37 | 2010 |
Is 3D integration an opportunity or just a hype? JF Li, CW Wu 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 541-543, 2010 | 37 | 2010 |
Raisin: Redundancy analysis algorithm simulation RF Huang, JC Yeh, JF Li, CW Wu IEEE Design & Test of Computers 24 (4), 386-396, 2007 | 37 | 2007 |
A built-in self-repair scheme for multiport RAMs TW Tseng, CH Wu, YJ Huang, JF Li, A Pao, K Chiu, E Chen 25th IEEE VLSI Test Symposium (VTS'07), 355-360, 2007 | 35 | 2007 |