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Tobias Scheipel
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System-aware performance monitoring unit for RISC-V architectures
T Scheipel, F Mauroner, M Baunach
2017 Euromicro Conference on Digital System Design (DSD), 86-93, 2017
82017
Smart mobility of the future–a challenge for embedded automotive systems
M Baunach, R Martins Gomes, M Malenko, F Mauroner, L Batista Ribeiro, ...
e & i Elektrotechnik und Informationstechnik 135 (4), 304-308, 2018
62018
papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping
T Scheipel, M Baunach
ICONS 2019-The Fourteenth International Conference on Systems, 20-25, 2019
32019
SmartOS: An OS Architecture for Sustainable Embedded Systems
T Scheipel, L Batista Ribeiro, T Sagaster, M Baunach
Tagungsband des FG-BS Frühjahrstreffens 2022, 2022
12022
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
T Scheipel, P Brungs, M Baunach
2021 24th Euromicro Conference on Digital System Design (DSD), 199-207, 2021
12021
papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software.
T Scheipel, M Baunach
SENSORNETS, 136-141, 2020
12020
Towards an Automated Printed Circuit Board Generation Concept for Embedded Systems
T Scheipel, M Baunach
International Journal on Advances in Systems and Measurements 12 (3&4), 236-246, 2019
12019
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
T Scheipel, F Angermair, MC Baunach
25th Euromicro Conference on Digital System Design: DSD 2022, 2022
2022
A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance
V Sivashanmugam, TP Scheipel, MC Baunach, B Adabala
International Conference on Computing and Applied Engineering, 2021
2021
papagenoReQ: Generation of Embedded Systems from Application Code Requirements
T Scheipel, M Baunach
2021 International Conference on Electrical, Communication, and Computer …, 2021
2021
FPGA-Based Debugging with Dynamic SignalSelection at Run-Time.
G Fiala, T Scheipel, W Neuwirth, M Baunach
Software Engineering (Workshops), 2020
2020
Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur
T Scheipel, F Mauroner, M Baunach
Logistik und Echtzeit, 69-78, 2017
2017
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