| System-aware performance monitoring unit for RISC-V architectures T Scheipel, F Mauroner, M Baunach 2017 Euromicro Conference on Digital System Design (DSD), 86-93, 2017 | 19 | 2017 |
| Smartos: An os architecture for sustainable embedded systems T Scheipel, L Batista Ribeiro, T Sagaster, M Baunach Gesellschaft für Informatik eV, 2022 | 7 | 2022 |
| Smart mobility of the future–a challenge for embedded automotive systems MC Baunach, RM Gomes, M Malenko, F Mauroner, LB Ribeiro, ... Elektrotechnik und Informationstechnik, 304-308, 2018 | 6 | 2018 |
| papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping T Scheipel, M Baunach ICONS 2019-The Fourteenth International Conference on Systems, 20-25, 2019 | 3 | 2019 |
| moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems T Scheipel, F Angermair, M Baunach 2022 25th Euromicro Conference on Digital System Design (DSD), 24-31, 2022 | 2 | 2022 |
| A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime T Scheipel, P Brungs, M Baunach 2021 24th Euromicro Conference on Digital System Design (DSD), 199-207, 2021 | 2 | 2021 |
| A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance V Sivashanmugam, T Scheipel, M Baunach, B Adabala 1st International Conference on Computing and Applied Engineering: ICCAE 2021, 2021 | 1 | 2021 |
| papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software. T Scheipel, M Baunach SENSORNETS, 136-141, 2020 | 1 | 2020 |
| Towards an Automated Printed Circuit Board Generation Concept for Embedded Systems T Scheipel, M Baunach International Journal on Advances in Systems and Measurements* 12 (3&4), 236-246, 2019 | 1 | 2019 |
| Formal Modeling and Verification of Low-Level AUTOSAR OS Specifications: Towards Portability and Correctness V Manjunath, T Scheipel, MC Baunach 40th ACM/SIGAPP Symposium On Applied Computing, SAC 2025, 2024 | | 2024 |
| Formal Specifications of Real-Time AUTOSAR-Compliant Operating Systems D Nagarajan, T Scheipel, MC Baunach Real-Time Networks and Systems, 2024 | | 2024 |
| opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs K Kanics, M Kissich, G Wirrer, T Scheipel, M Baunach WiPiEC Journal-Works in Progress in Embedded Computing Journal 10 (2), 2024 | | 2024 |
| Stitching FPGA Fabrics with FABulous and OpenLane 2 L Moser, M Kissich, T Scheipel, M Baunach Proceedings of the 21st ACM International Conference on Computing Frontiers …, 2024 | | 2024 |
| Fair and Starvation-Free Spinlock for Real-Time AUTOSAR systems: M-HLP D Nagarajan, T Scheipel, M Baunach Proceedings of the 39th ACM/SIGAPP Symposium on Applied Computing, 436-445, 2024 | | 2024 |
| One Solution to Rule Them All: ATTEST as Unified Testing Solution for Programming Courses M Kissich, K Kanics, K Weinbauer, T Scheipel, M Baunach Gesellschaft für Informatik eV, 2023 | | 2023 |
| Advances in Dynamic and Reconfigurable Embedded Systems Design T Scheipel | | 2022 |
| papagenoReQ: Generation of Embedded Systems from Application Code Requirements T Scheipel, M Baunach 2021 International Conference on Electrical, Communication, and Computer …, 2021 | | 2021 |
| FPGA-Based Debugging with Dynamic SignalSelection at Run-Time. G Fiala, T Scheipel, W Neuwirth, M Baunach Software Engineering (Workshops), 2020 | | 2020 |
| Mobilität der Zukunft–eine Herausforderung für eingebettete Systeme in Fahrzeugen M Baunach, R Martins Gomes, M Malenko, F Mauroner, L Batista Ribeiro, ... e & i Elektrotechnik und Informationstechnik 135, 304-308, 2018 | | 2018 |
| Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur T Scheipel, F Mauroner, M Baunach Logistik und Echtzeit: Echtzeit 2017, 69-78, 2017 | | 2017 |
Marcel BaunachProfessor for Embedded Automotive Systems, Graz University of TechnologyVerified email at tugraz.at
