| Exploiting transistor-level reconfiguration to optimize combinational circuits M Raitza, A Kumar, M Völp, D Walter, J Trommer, T Mikolajick, WM Weber Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 58 | 2017 |
| 10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS B Noethen, O Arnold, EP Adeva, T Seifert, E Fischer, S Kunze, E Matúš, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 57 | 2014 |
| A fast-locking ADPLL with instantaneous restart capability in 28-nm CMOS technology S Höppner, S Haenzsche, G Ellguth, D Walter, H Eisenreich, R Schüffny IEEE Transactions on Circuits and Systems II: Express Briefs 60 (11), 741-745, 2013 | 54 | 2013 |
| A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS D Walter, S Höppner, H Eisenreich, G Ellguth, S Henker, S Hänzsche, ... 2012 IEEE International Solid-State Circuits Conference, 180-182, 2012 | 51 | 2012 |
| The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing S Höppner, Y Yan, A Dixius, S Scholze, J Partzsch, M Stolba, F Kelber, ... arXiv preprint arXiv:2103.08392, 2021 | 38 | 2021 |
| A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications S Haas, T Seifert, B Nöthen, S Scholze, S Höppner, A Dixius, EP Adeva, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 37 | 2017 |
| A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology S Hoppner, H Eisenreich, S Henker, D Walter, G Ellguth, R Schuffny IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (3), 566-570, 2012 | 35 | 2012 |
| A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs S Rai, A Rupani, D Walter, M Raitza, A Heinzig, T Baldauf, J Trommer, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 605-608, 2018 | 34 | 2018 |
| Adaptive body bias aware implementation for ultra-low-voltage designs in 22FDX technology S Höppner, H Eisenreich, D Walter, A Scharfe, A Oefelein, F Schraut, ... IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2159-2163, 2019 | 29 | 2019 |
| How to achieve world-leading energy efficiency using 22FDX with adaptive body biasing on an Arm Cortex-M4 IoT SoC S Höppner, H Eisenreich, D Walter, U Steeb, ASC Dmello, R Sinkwitz, ... ESSDERC 2019-49th European Solid-State Device Research Conference (ESSDERC …, 2019 | 25 | 2019 |
| An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS S Höppner, D Walter, T Hocker, S Henker, S Hänzsche, D Sausner, ... IEEE Journal of Solid-State Circuits 50 (3), 749-762, 2015 | 24 | 2015 |
| A 16-Channel Fully Configurable Neural SoC With 1.52 W/Ch Signal Acquisition, 2.79 W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural … SMA Zeinolabedin, FM Schüffny, R George, F Kelber, H Bauer, S Scholze, ... IEEE Transactions on Biomedical Circuits and Systems 16 (1), 94-107, 2022 | 21 | 2022 |
| An MPSoC for energy-efficient database query processing S Haas, O Arnold, B Nöthen, S Scholze, G Ellguth, A Dixius, S Höppner, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 20 | 2016 |
| Hardware implementation of an opc ua server for industrial field devices H Bauer, S Höppner, C Iatrou, Z Charania, S Hartmann, SU Rehman, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (11 …, 2021 | 13 | 2021 |
| Reconfigurable germanium transistors with low source-drain leakage for secure and energy-efficient doping-free complementary circuits J Trommer, A Heinzig, S Slesazeck, U Mühle, M Löffler, D Walter, C Mayr, ... 2017 75th Annual Device Research Conference (DRC), 1-2, 2017 | 13 | 2017 |
| A 0.55 V 6.3 uW/MHz arm cortex-M4 MCU with adaptive reverse body bias and single rail SRAM D Walter, A Scharfe, A Oefelein, F Schraut, H Bauer, F Csaszar, ... 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2020 | 12 | 2020 |
| An energy efficient multi-bit TSV transmitter using capacitive coupling J Görner, S Höppner, D Walter, M Haas, D Plettemeier, R Schüffny 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 8 | 2014 |
| ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data M Jobst, J Partzsch, C Liu, L Guo, D Walter, SU Rehman, S Scholze, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 6 | 2022 |
| Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project F Ellinger, T Mikolajick, G Fettweis, D Hentschel, S Kolodinski, ... The European Physical Journal-Applied Physics 63 (1), 14402, 2013 | 5 | 2013 |
| Efficient compensation of delay variations in high-speed network-on-chip data links S Höppner, D Walter, H Eisenreich, R Schüffny 2010 International Symposium on System on Chip, 55-58, 2010 | 5 | 2010 |
