| On the detectability of scan chain internal faults an industrial case study F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 26th IEEE VLSI Test Symposium (vts 2008), 79-84, 2008 | 57 | 2008 |
| Detection of internal stuck-open faults in scan chains F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2008 IEEE International Test Conference, 1-10, 2008 | 29 | 2008 |
| Improving the detectability of resistive open faults in scan cells F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009 | 21 | 2009 |
| Silicon evaluation of cell-aware ATPG tests and small delay tests F Yang, S Chakravarty, A Gunda, N Wu, J Ning 2014 IEEE 23rd Asian Test Symposium, 101-106, 2014 | 16 | 2014 |
| Silicon evaluation of faster than at-speed transition delay tests S Chakravarty, N Devta-Prasanna, A Gunda, J Ma, F Yang, H Guo, R Lai, ... 2012 IEEE 30th VLSI Test Symposium (VTS), 80-85, 2012 | 14 | 2012 |
| Detectability of internal bridging faults in scan chains F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2009 Asia and South Pacific Design Automation Conference, 678-683, 2009 | 12 | 2009 |
| Dft technique to apply a variable scan clock including a scan clock modifier on an ic S Chakravarty, NB Devta-Prasa, A Gunda, F Yang US Patent App. 12/337,629, 2010 | 7 | 2010 |
| Detection of transistor stuck-open faults in asynchronous inputs of scan cells F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 7 | 2008 |
| An enhanced logic bist architecture for online testing F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2008 14th IEEE International On-Line Testing Symposium, 10-15, 2008 | 7 | 2008 |
| A novel method for fast identification of peak current during test W Zhao, S Chakravarty, J Ma, N Devta-Prasanna, F Yang, M Tehranipoor 2012 IEEE 30th VLSI Test Symposium (VTS), 191-196, 2012 | 5 | 2012 |
| Testing of latch based embedded arrays using scan tests F Yang, S Chakravarty 2010 IEEE International Test Conference, 1-10, 2010 | 5 | 2010 |
| Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit S Chakravarty, NB Devta-Prasa, A Gunda, F Yang US Patent 8,418,008, 2013 | 3 | 2013 |
| Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit S Chakravarty, NB Devta-Prasa, A Gunda, F Yang US Patent 8,418,008, 2013 | 3 | 2013 |
| Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit S Chakravarty, NB Devta-Prasa, A Gunda, F Yang US Patent 8,418,008, 2013 | 3 | 2013 |
| Enhanced logic built-in self-test module and method of online system testing employing the same S Chakravarty, N Devta-Prasanna, F Yang US Patent 7,802,159, 2010 | 2 | 2010 |
| An Automated Propagation Approach that Promotes and Demotes the Timing Exception Between Hierarchical Blocks and Flat Design W Chao, Y Xu, F Yang, G Huang 2023 International Symposium of Electronics Design Automation (ISEDA), 102-105, 2023 | | 2023 |
| New tests and test methodologies for scan cell internal faults F Yang The University of Iowa, 2009 | | 2009 |
Narendra Devta-PrasannaGoogleBestätigte E-Mail-Adresse bei google.com
