| Statistical fault injection: Quantified error and confidence R Leveugle, A Calvez, P Maistri, P Vanhauwaert 2009 Design, Automation & Test in Europe Conference & Exhibition, 502-506, 2009 | 486 | 2009 |
| Error analysis and detection procedures for a hardware implementation of the advanced encryption standard G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri IEEE transactions on Computers 52 (4), 492-505, 2003 | 444 | 2003 |
| Double-data-rate computation as a countermeasure against fault analysis P Maistri, R Leveugle IEEE Transactions on Computers 57 (11), 1528-1539, 2008 | 134 | 2008 |
| Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA G Canivet, P Maistri, R Leveugle, J Clédière, F Valette, M Renaudin Journal of cryptology 24, 247-268, 2011 | 106 | 2011 |
| A parity code based fault detection for an implementation of the advanced encryption standard G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2002 | 86 | 2002 |
| An efficient hardware-based fault diagnosis scheme for AES: performances and cost G Bertoni, L Breveglieri, I Koren, P Maistri 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2004 | 78 | 2004 |
| Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ... 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018 | 62 | 2018 |
| Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard L Breveglieri, I Koren, P Maistri 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 61 | 2005 |
| An operation-centered approach to fault detection in symmetric cryptography ciphers L Breveglieri, I Koren, P Maistri IEEE Transactions on Computers 56 (5), 635-649, 2007 | 59 | 2007 |
| Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 44 | 2003 |
| On the propagation of faults and their detection in a hardware implementation of the advanced encryption standard G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri Proceedings IEEE International Conference on Application-Specific Systems …, 2002 | 39 | 2002 |
| A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks A Papadimitriou, D Hély, V Beroulle, P Maistri, R Leveugle 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 35 | 2014 |
| A novel double-data-rate AES architecture resistant against fault injection P Maistri, P Vanhauwaert, R Leveugle Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007), 54-61, 2007 | 33 | 2007 |
| Countermeasures against EM analysis for a secured FPGA-based AES implementation P Maistri, S Tiran, P Maurine, I Koren, R Leveugle 2013 International Conference on Reconfigurable Computing and FPGAs …, 2013 | 26 | 2013 |
| Countermeasures against fault attacks: The good, the bad, and the ugly P Maistri 2011 IEEE 17th International On-Line Testing Symposium, 134-137, 2011 | 25 | 2011 |
| Electromagnetic analysis and fault injection onto secure circuits P Maistri, R Leveugle, L Bossuet, A Aubert, V Fischer, B Robisson, ... 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014 | 24 | 2014 |
| Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections P Maistri, P Vanhauwaert, R Leveugle 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007 | 24 | 2007 |
| Laser-induced fault effects in security-dedicated circuits R Leveugle, P Maistri, P Vanhauwaert, F Lu, G Di Natale, ML Flottes, ... 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014 | 22 | 2014 |
| A note on error detection in an RSA architecture by means of residue codes L Breveglieri, P Maistri, I Koren 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2 pp., 2006 | 19 | 2006 |
| Polynomial multipliers for fully homomorphic encryption on FPGA C Jayet-Griffon, MA Cornelie, P Maistri, PH Elbaz-Vincent, R Leveugle 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 17 | 2015 |
