| Task mapping in heterogeneous MPSoCs for system level design K Vivekanandarajah, SK Pilakkat 13th IEEE International Conference on Engineering of Complex Computer …, 2008 | 25 | 2008 |
| Dynamic filter cache for low power instruction memory hierarchy K Vivekanandarajah, T Srikanthan, S Bhattacharyya Euromicro Symposium on Digital System Design, 2004. DSD 2004., 607-610, 2004 | 18 | 2004 |
| Custom instruction filter cache synthesis for low-power embedded systems K Vivekanandarajah, T Srikanthan 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 151-157, 2005 | 13 | 2005 |
| Incorporating pattern prediction technique for energy efficient filter cache design K Vivekanandarajah, T Srikanthan, S Bhattacharya, PV Kannan The 3rd IEEE International Workshop on System-on-Chip for Real-Time …, 2003 | 11 | 2003 |
| Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures K Vivekanandarajah, T Srikanthan, S Bhattacharyya ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 9 | 2004 |
| Energy-delay efficient filter cache hierarchy using pattern prediction scheme K Vivekanandarajah, T Srikanthan, S Bhattacharyya IEE Proceedings-Computers and Digital Techniques 151 (2), 141-146, 2004 | 8 | 2004 |
| Profile directed instruction cache tuning for embedded systems K Vivekanandarajah, T Srikanthan, CT Clarke IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006 | 7 | 2006 |
| A novel static prediction scheme for filter cache structures K Vivekanandarajah, T Srikanthan, CT Clarke, S Bhattacharyya IEICE transactions on electronics 87 (4), 543-548, 2004 | 3 | 2004 |
| Area and power efficient pattern prediction architecture for filter cache access prediction in the instruction memory hierarchy S Bhattacharyya, T Srikanthan, K Vivekanandarajah 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and …, 2005 | 2 | 2005 |
| Customizable instruction cache hierarchy for embedded systems K Vivekanandarajah | 2 | 2005 |
| Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design. K Vivekanandarajah, T Srikanthan, CT Clarke, S Bhattacharyya Embedded Systems and Applications, 210-215, 2003 | 2 | 2003 |
| Design considerations for multi-radio co-existence on asynchronous processors using LAD extensions D Guha, K Vivekanandarajah, T Srikanthan 2006 40th Annual Conference on Information Sciences and Systems, 413-413, 2006 | | 2006 |
C T ClarkeUniversity of BathVerified email at bath.ac.uk
C T ClarkeUniversity of BathVerified email at bath.ac.uk