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IEEE Transactions on Electron Devices 61 (5), 1284-1291, 2014
133 2014 First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching YQ Wu, RS Wang, T Shen, JJ Gu, PD Ye
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
109 2009 Analog/RF performance of Si nanowire MOSFETs and the impact of process variation R Wang, J Zhuge, RU Huang, YU Tian, H Xiao, L Zhang, C Li, X Zhang, ...
IEEE transactions on Electron Devices 54 (6), 1288-1294, 2007
105 2007 GaSb Inversion-Mode PMOSFETs With Atomic-Layer-Deposited as Gate Dielectric M Xu, R Wang, DY Peide
IEEE electron device letters 32 (7), 883-885, 2011
99 2011 Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs J Zhuge, R Wang, R Huang, Y Tian, L Zhang, DW Kim, D Park, Y Wang
IEEE Electron Device Letters 30 (1), 57-60, 2008
95 2008 High-speed black phosphorus field-effect transistors approaching ballistic limit X Li, Z Yu, X Xiong, T Li, T Gao, R Wang, R Huang, Y Wu
Science advances 5 (6), eaau3194, 2019
94 2019 Impacts of random telegraph noise (RTN) on digital circuits M Luo, R Wang, S Guo, J Wang, J Zou, R Huang
IEEE Transactions on Electron Devices 62 (6), 1725-1732, 2014
90 2014 New self-aligned silicon nanowire transistors on bulk substrate fabricated by epi-free compatible CMOS technology: Process integration, experimental characterization of carrier … Y Tian, R Huang, Y Wang, J Zhuge, R Wang, J Liu, X Zhang, Y Wang
2007 IEEE International Electron Devices Meeting, 895-898, 2007
83 2007 High Performance Deep-Submicron Inversion-Mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/µm: New HBr pretreatment and channel engineering YQ Wu, M Xu, RS Wang, O Koybasi, PD Ye
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
82 2009 Experimental investigations on carrier transport in Si nanowire transistors: Ballistic efficiency and apparent mobility R Wang, H Liu, R Huang, J Zhuge, L Zhang, DW Kim, X Zhang, D Park, ...
IEEE transactions on electron devices 55 (11), 2960-2967, 2008
82 2008 Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs J Zou, Q Xu, J Luo, R Wang, R Huang, Y Wang
IEEE transactions on electron devices 58 (10), 3379-3387, 2011
74 2011 Challenges of 22 nm and beyond CMOS technology R Huang, HM Wu, JF Kang, DY Xiao, XL Shi, X An, Y Tian, RS Wang, ...
Science in China Series F: Information Sciences 52 (9), 1491-1533, 2009
66 2009 Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device variability R Wang, X Jiang, T Yu, J Fan, J Chen, DZ Pan, R Huang
IEEE transactions on electron devices 60 (11), 3676-3682, 2013
65 2013 New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability Z Yu, J Zhang, R Wang, S Guo, C Liu, R Huang
2017 IEEE International Electron Devices Meeting (IEDM), 7.2. 1-7.2. 4, 2017
64 2017 Investigation on variability in metal-gate Si nanowire MOSFETs: Analysis of variation sources and experimental characterization R Wang, J Zhuge, R Huang, T Yu, J Zou, DW Kim, D Park, Y Wang
IEEE transactions on electron devices 58 (8), 2317-2325, 2011
64 2011 Senputing: An ultra-low-power always-on vision perception chip featuring the deep fusion of sensing and computing H Xu, N Lin, L Luo, Q Wei, R Wang, C Zhuo, X Yin, F Qiao, H Yang
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 232-243, 2021
59 2021 Investigation of parasitic effects and design optimization in silicon nanowire MOSFETs for RF applications J Zhuge, R Wang, R Huang, X Zhang, Y Wang
IEEE transactions on electron devices 55 (8), 2142-2147, 2008
58 2008 Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective Q Huang, R Huang, C Wu, H Zhu, C Chen, J Wang, L Guo, R Wang, L Ye, ...
2014 IEEE International Electron Devices Meeting, 13.3. 1-13.3. 4, 2014
56 2014 TD-SRAM: Time-domain-based in-memory computing macro for binary neural networks J Song, Y Wang, M Guo, X Ji, K Cheng, Y Hu, X Tang, R Wang, R Huang
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (8), 3377-3387, 2021
54 2021 Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part I–modeling and simulation method X Jiang, R Wang, T Yu, J Chen, R Huang
IEEE Transactions on electron devices 60 (11), 3669-3675, 2013
48 2013