| An analysis of accelerator coupling in heterogeneous architectures EG Cota, P Mantovani, G Di Guglielmo, LP Carloni 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015 | 60 | 2015 |
| A switched-inductor integrated voltage regulator with nonlinear feedback and network-on-chip load in 45 nm SOI N Sturcken, M Petracca, S Warren, P Mantovani, LP Carloni, ... IEEE Journal of Solid-State Circuits 47 (8), 1935-1945, 2012 | 56 | 2012 |
| COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators L Piccolboni, P Mantovani, GD Guglielmo, LP Carloni ACM Transactions on Embedded Computing Systems (TECS) 16 (5s), 1-22, 2017 | 31 | 2017 |
| An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems P Mantovani, EG Cota, K Tien, C Pilato, G Di Guglielmo, K Shepard, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 30 | 2016 |
| High-level synthesis of accelerators in embedded scalable platforms P Mantovani, G Di Guglielmo, LP Carloni 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 204-211, 2016 | 30 | 2016 |
| Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip P Mantovani, EG Cota, C Pilato, G Di Guglielmo, LP Carloni Proceedings of the International Conference on Compilers, Architectures and …, 2016 | 28 | 2016 |
| Accelerator memory reuse in the dark silicon era EG Cota, P Mantovani, M Petracca, MR Casu, LP Carloni IEEE Computer Architecture Letters 13 (1), 9-12, 2012 | 28 | 2012 |
| System-level optimization of accelerator local memory for heterogeneous systems-on-chip C Pilato, P Mantovani, G Di Guglielmo, LP Carloni IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 24 | 2016 |
| System-level memory optimization for high-level synthesis of component-based SoCs C Pilato, P Mantovani, G Di Guglielmo, LP Carloni Proceedings of the 2014 International Conference on Hardware/Software …, 2014 | 19 | 2014 |
| Accelerators and coherence: An SoC perspective D Giri, P Mantovani, LP Carloni IEEE Micro 38 (6), 36-45, 2018 | 17 | 2018 |
| NoC-based support of heterogeneous cache-coherence models for accelerators D Giri, P Mantovani, LP Carloni 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018 | 16 | 2018 |
| Broadening the exploration of the accelerator design space in embedded scalable platforms L Piccolboni, P Mantovani, G Di Guglielmo, LP Carloni 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 12 | 2017 |
| ESP4ML: platform-based design of systems-on-chip for embedded machine learning D Giri, KL Chiu, G Di Guglielmo, P Mantovani, LP Carloni 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 11 | 2020 |
| On the design of scalable and reusable accelerators for big data applications C Pilato, Q Xu, P Mantovani, G Di Guglielmo, LP Carloni Proceedings of the ACM International Conference on Computing Frontiers, 406-411, 2016 | 8 | 2016 |
| Agile SoC development with open ESP P Mantovani, D Giri, G Di Guglielmo, L Piccolboni, J Zuckerman, EG Cota, ... 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2020 | 6 | 2020 |
| System-level design of networks-on-chip for heterogeneous systems-on-chip YJ Yoon, P Mantovani, LP Carloni 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-6, 2017 | 5 | 2017 |
| Teaching heterogeneous computing with system-level design methods LP Carloni, EG Cota, GD Guglielmo, D Giri, J Kwon, P Mantovani, ... Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019 | 4 | 2019 |
| Exploiting private local memories to reduce the opportunity cost of accelerator integration EG Cota, P Mantovani, LP Carloni Proceedings of the 2016 International Conference on Supercomputing, 1-12, 2016 | 4 | 2016 |
| Ariane+ NVDLA: seamless third-party IP integration with ESP D Giri, KL Chiu, G Eichler, P Mantovani, N Chandramoorth, LP Carloni Workshop on Computer Architecture Research with RISC-V (CARRV), 2020 | 3 | 2020 |
| Towards a complete methodology for synthesizing bundled-data asynchronous circuits on FPGAs K Bhardwaj, P Mantovani, LP Carloni, SM Nowick 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 3 | 2019 |
Luca CarloniProfessor of Computer Science, Columbia UniversityBestätigte E-Mail-Adresse bei cs.columbia.edu
