| Multi objective analysis of NCL threshold gates with return to zero protocols J Sudhakar, AM Prasad, AK Panda IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) 10 (3 …, 2015 | 9 | 2015 |
| Low power aware standard cells using dual rail multi threshold null convention logic methodology M Suresh, AK Panda, J Sudhakar Microprocessors and Microsystems 68, 28-33, 2019 | 7 | 2019 |
| Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic S Jyothula, K Sushma Circuit World 43 (2), 72-79, 2017 | 6 | 2017 |
| Low power aware pulse triggered flip flops using modified clock gating approaches S Jyothula World Journal of Engineering 15 (6), 792-803, 2018 | 4 | 2018 |
| A Study on Self Timed Approach for Design of Low Power Circuits at Nano Scale JS G. Vandana Devi International Journal of Advances in Electrical and Electronics Engineering …, 2015 | 4* | 2015 |
| Biotechnological approach of in vitro production of capsaicin GA Ravishankar, JT Sudhakar, LV Venkataraman Proceedings of the national seminar on post harvest technology of spices …, 1993 | 4 | 1993 |
| A novel ripple borrow subtractor cell design using asynchronous methodology J Sudhakar, C Padmavani 2017 International Conference on Inventive Communication and Computational …, 2017 | 3 | 2017 |
| GFCG: Glitch free combinational clock gating approach in nanometer VLSI circuits J Sudhakar, AM Prasad, AK Panda 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 3 | 2015 |
| Design of 64 bit SRAM using lector technique for low leakage power with read and write enable Y Alekhya, J Sudhakar IOSR Journal of VLSI and Signal Processing (IOSRJVSP) 7, 10-19, 2017 | 2 | 2017 |
| Energy Aware IP Shifter for DSP Processors using MTD3L Asynchronous Approach JS K. Sushma IOSR Journal of VLSI and Signal Processing 6 (06), 41-47, 2016 | 2 | 2016 |
| An Alternative Delay Insensitive Paradigm for Low Power Synchronous Digital Circuits JS K. Sushma International Journal of Electrical and Electronics Engineers 8 (2), 172-183, 2016 | 2 | 2016 |
| FPGA implementation of PN-sequence generator with binary chaos synchronization J Sudhakar, FB Shaik, J Hari 2014 International Conference on Electronics and Communication Systems …, 2014 | 2 | 2014 |
| Glitch Power Minimization Techniques in Low Power VLSI Circuits J Sudhakar, KT Rao, B Suresh IJETAE 2 (11), 2012 | 2 | 2012 |
| Behavior of Self Timed Null Convention Logic Circuits with Threshold Variations J Sudhakar, AM Prasad, AK Panda international Journal of Emerging Trends in Engineering Research (IJETER) 3 …, 0 | 2 | |
| Optimization of Dielectric Material and Gradings of the Post-type FGM Spacer for a Multi-Objective Function A Mishra, GVN Kumar, J Sudhakar, VN Kumar, A Nagaraju, V Rafi International Symposium on Sustainable Energy and Technological Advancements …, 2023 | 1 | 2023 |
| A Dual-Rail Delay-Insensitive IEEE-754 Single-Precision Null Convention Floating Point Multiplier for Low-Power Applications J Sudhakar, Y Alekhya, KS Syamala Innovations in Electronics and Communication Engineering: Proceedings of the …, 2017 | 1 | 2017 |
| Design of energy efficient dual spacer delay insensitive ripple carry adder with better slew rate J Sudhakar, K Sushma Int J Eng Technol 8, 2970-2978, 2016 | 1 | 2016 |
| Exhaustive analysis & behavior of nanometer MOSFET for threshold voltage variations J Sudhakar, AM Prasad, AK Panda 2015 3rd International Conference on Signal Processing, Communication and …, 2015 | 1 | 2015 |
| Design Of Power Efficient 12T Sram Using Adiabatic Technique For Charge Recovery Application J Sudhakar, SK Reddy, G Srinivas | | 2022 |
| DESIGN OF HIGH THROUGHPUT ADD COMPARE AND SELECT UNIT FOR LOW POWER VITERBI DECODER S Jyothula, VS Ganta, RB Chukka INFORMATION TECHNOLOGY IN INDUSTRY 9 (1), 954-960, 2021 | | 2021 |
Ajit Kumar PandaElectronics Center of ExcellenceBestätigte E-Mail-Adresse bei ieee.org
