PLL low pass filter design considering unified specification constraints B Jiang, T Xia, G Wang
Analog Integrated Circuits and Signal Processing 80, 113-120, 2014
21 2014 ADPLL design parameters determinations through noise modeling B Jiang, T Xia
Integration 48, 138-145, 2015
13 2015 A 3-wafer-stacked hybrid 15MPixel CIS+ 1 MPixel EVS with 4.6 GEvent/s readout, in-pixel TDC and on-chip ISP and ESP function M Guo, S Chen, Z Gao, W Yang, P Bartkovjak, Q Qin, X Hu, D Zhou, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 90-92, 2023
10 2023 Model analysis of multi-finger MOSFET layout in ring oscillator design B Jiang, T Xia
2011 12th International Symposium on Quality Electronic Design, 1-6, 2011
10 2011 ADPLL variables determinations based on phase noise, spur and locking time B Jiang, T Xia
2012 IEEE International SOC Conference, 39-44, 2012
9 2012 A quad-mode DCO for multi-standard communication application B Jiang, T Xia
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2229-2232, 2015
6 2015 A wide band adaptive all digital phase locked loop with self jitter measurement and calibration B Jiang
The University of Vermont and State Agricultural College, 2016
1 2016 A Three-Wafer-Stacked Hybrid 15-MPixel CIS M Guo, S Chen, Z Gao, W Yang, P Bartkovjak, Q Qin, X Hu, D Zhou, ...
IEEE Journal of Solid-State Circuits, 2023
2023 An Analytical Model for All-Digital PLL Phase Noise Characterization B Jiang, T Xia
IEEE North Atlantic Test Workshop, 2011
2011 