| On the functional test of the register forwarding and pipeline interlocking unit in pipelined processors P Bernardi, R Cantoro, L Ciganda, B Du, E Sánchez, MS Reorda, ... 2013 14th International Workshop on Microprocessor Test and Verification, 52-57, 2013 | 17 | 2013 |
| Online test of control flow errors: A new debug interface-based approach B Du, MS Reorda, L Sterpone, L Parra, M Portela-García, A Lindoso, ... IEEE Transactions on Computers 65 (6), 1846-1855, 2015 | 16 | 2015 |
| A new hybrid nonintrusive error-detection technique using dual control-flow monitoring L Parra, A Lindoso, M Portela-Garcia, L Entrena, B Du, MS Reorda, ... IEEE Transactions on Nuclear Science 61 (6), 3236-3243, 2014 | 14 | 2014 |
| An extended model to support detailed GPGPU reliability analysis B Du, JER Condia, MS Reorda 2019 14th International Conference on Design & Technology of Integrated …, 2019 | 11 | 2019 |
| About the functional test of the GPGPU scheduler B Du, JER Condia, MS Reorda, L Sterpone 2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018 | 11 | 2018 |
| Analysis and mitigation of single event effects on flash-based FPGAs L Sterpone, B Du 2014 19th IEEE European Test Symposium (ETS), 1-6, 2014 | 11 | 2014 |
| On the prediction of radiation-induced SETs in flash-based FPGAs S Azimi, B Du, L Sterpone Microelectronics Reliability 64, 230-234, 2016 | 8 | 2016 |
| A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs S Azimi, B Du, L Sterpone, DM Codinachs, R Grimoldi, L Cattaneo Integration 67, 73-81, 2019 | 7 | 2019 |
| Ultrahigh energy heavy ion test beam on Xilinx Kintex-7 SRAM-based FPGA B Du, L Sterpone, S Azimi, DM Codinachs, V Ferlet-Cavrois, CB Polo, ... IEEE Transactions on Nuclear Science 66 (7), 1813-1819, 2019 | 7 | 2019 |
| On the reliability of convolutional neural network implementation on SRAM-based FPGA B Du, S Azimi, C De Sio, L Bozzoli, L Sterpone 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019 | 6 | 2019 |
| Exploiting the debug interface to support on-line test of control flow errors B Du, MS Reorda, L Sterpone, L Parra, M Portela-García, A Lindoso, ... 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 98-103, 2013 | 6 | 2013 |
| FlexGripPlus: An improved GPGPU model to support reliability analysis JER Condia, B Du, MS Reorda, L Sterpone Microelectronics Reliability 109, 113660, 2020 | 5 | 2020 |
| FPGA-controlled PCBA power-on self-test using processor's debug features B Du, E Sánchez, MS Reorda, JP Acle, A Tsertov 2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016 | 5 | 2016 |
| Fault-tolerance techniques for soft-core processors using the trace interface L Entrena, A Lindoso, M Portela-Garcia, L Parra, B Du, MS Reorda, ... FPGAs and Parallel Architectures for Aerospace Applications, 293-306, 2016 | 5 | 2016 |
| Radiation-induced single event transients modeling and testing on nanometric flash-based technologies L Sterpone, B Du, S Azimi Microelectronics Reliability 55 (9-10), 2087-2091, 2015 | 5 | 2015 |
| Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAs B Du, M Desogus, L Sterpone 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics …, 2015 | 5 | 2015 |
| A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors P Bernardi, D Boyang, L Ciganda, E Sánchez, MS Reorda, M Grosso, ... 2013 8th IEEE Design and Test Symposium, 1-6, 2013 | 5 | 2013 |
| Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect C De Sio, S Azimi, L Sterpone, B Du IEEE Access 7, 140182-140189, 2019 | 4 | 2019 |
| On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs S Azimi, L Sterpone, B Du, L Boragno Microelectronics Reliability 88, 936-940, 2018 | 4 | 2018 |
| Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs L Sterpone, S Azimi, B Du, DM Codinachs, R Grimoldi Proceedings of the on Great Lakes Symposium on VLSI 2017, 203-208, 2017 | 4 | 2017 |
Luca SterponePolitecnico di TorinoVerified email at polito.it
