| Exact timing analysis for asynchronous systems W Hua, R Manohar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 21 | 2017 |
| Cyclone: A static timing and power engine for asynchronous circuits W Hua, YS Lu, K Pingali, R Manohar 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020 | 15 | 2020 |
| An open-source eda flow for asynchronous logic S Ataei, W Hua, Y Yang, R Manohar, YS Lu, J He, S Maleki, K Pingali IEEE Design & Test 38 (2), 27-37, 2021 | 14 | 2021 |
| Toward a digital flow for asynchronous VLSI systems S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, R Manohar 2nd Workshop on Open-Source EDA Technology (WOSET), 0 | 1 | |
| Cyclone: The First Integrated Timing and Power Engine for Asynchronous Systems W Hua Cornell University, 2020 | | 2020 |
| Number-Theoretic Random Walks Project Report Y Chen, W Hua, N Monaikul, T Zhang, MT Phaovibul, AJ Hildebrand | | 2013 |
| interact: An Interactive Design Environment for Asynchronous Logic J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, R Manohar | | |
| A Digital Flow for Asynchronous VLSI Systems: Status Update U Agarwal, S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, ... | | |
| ParallelClosure: A Parallel Design Optimizer for Timing Closure YS Lu, W Hua, R Manohar, K Pingali | | |
| Parallel Tools for Asynchronous VLSI Systems YS Lu, S Ataei, J He, W Hua, S Maleki, Y Yang, M Burtscher, K Pingali, ... | | |
