20 Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency SK Tolpygo, D Yohannes, RT Hunt, JA Vivalda, D Donnelly, D Amparo, ... IEEE transactions on applied superconductivity 17 (2), 946-951, 2007 | 84 | 2007 |
System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits SK Tolpygo, D Amparo, R Hunt, J Vivalda, D Yohannes US Patent 8,437,818, 2013 | 55 | 2013 |
System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits SK Tolpygo, D Amparo, R Hunt, J Vivalda, D Yohannes US Patent 8,301,214, 2012 | 42 | 2012 |
RSFQ/ERSFQ cell library with improved circuit optimization, timing verification, and test characterization A Inamdar, D Amparo, B Sahoo, J Ren, A Sahu IEEE Transactions on Applied Superconductivity 27 (4), 1-9, 2017 | 36 | 2017 |
Planarized, extendible, multilayer fabrication process for superconducting electronics DT Yohannes, RT Hunt, JA Vivalda, D Amparo, A Cohen, IV Vernik, ... IEEE Transactions on Applied Superconductivity 25 (3), 1-5, 2014 | 32 | 2014 |
Fabrication-process-induced variations of Nb/Al/AlOx/Nb Josephson junctions in superconductor integrated circuits SK Tolpygo, D Amparo Superconductor Science and Technology 23 (3), 034024, 2010 | 28 | 2010 |
Plasma process-induced damage to Josephson tunnel junctions in superconducting integrated circuits SK Tolpygo, D Amparo, A Kirichenko, D Yohannes Superconductor Science and Technology 20 (11), S341, 2007 | 28 | 2007 |
Electrical stress effect on Josephson tunneling through ultrathin AlOx barrier in Nb/Al/AlOx/Nb junctions SK Tolpygo, D Amparo Journal of Applied Physics 104 (6), 2008 | 25 | 2008 |
Effects of adaptive DC biasing on operational margins in ERSFQ circuits C Shawawreh, D Amparo, J Ren, M Miller, MY Kamkar, A Sahu, ... IEEE Transactions on Applied Superconductivity 27 (4), 1-6, 2017 | 22 | 2017 |
Timing characterization for RSFQ cell library D Amparo, ME Çelik, S Nath, JP Cerqueira, A Inamdar IEEE Transactions on Applied Superconductivity 29 (5), 1-9, 2019 | 20 | 2019 |
Improved model-to-hardware correlation for superconductor integrated circuits A Inamdar, J Ren, D Amparo IEEE Transactions on Applied Superconductivity 25 (3), 1-8, 2014 | 19 | 2014 |
Diffusion stop-layers for superconducting integrated circuits and qubits with Nb-based Josephson junctions SK Tolpygo, D Amparo, RT Hunt, JA Vivalda, DT Yohannes IEEE transactions on applied superconductivity 21 (3), 119-125, 2010 | 19 | 2010 |
Process-Induced Variability ofJunctions in Superconductor IntegratedCircuits and Protection Against It SK Tolpygo, D Amparo, DT Yohannes, M Meckbach, AF Kirichenko IEEE transactions on applied superconductivity 19 (3), 135-139, 2009 | 18 | 2009 |
Experimental investigation of ERSFQ circuit for parallel multibit data transmission TV Filippov, D Amparo, MY Kamkar, J Walter, AF Kirichenko, ... 2017 16th International Superconductive Electronics Conference (ISEC), 1-4, 2017 | 13 | 2017 |
Subgap Leakage in - Josephson Junctions and Run-to-Run Reproducibility: Effects of Oxidation Chamber and Film Stress SK Tolpygo, DJC Amparo, RT Hunt, JA Vivalda, DT Yohannes IEEE transactions on applied superconductivity 23 (3), 1100305-1100305, 2012 | 13 | 2012 |
Fabrication process development for superconducting VLSI circuits: Minimizing plasma charging damage SK Tolpygo, D Amparo Journal of Physics: Conference Series 97 (1), 012227, 2008 | 13 | 2008 |
Investigation of the Role of H in Fabrication-Process- Induced Variations of Josephson Junctions D Amparo, SK Tolpygo IEEE transactions on applied superconductivity 21 (3), 126-130, 2010 | 12 | 2010 |
System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits SK Tolpygo, D Amparo, R Hunt, J Vivalda, D Yohannes US Patent 9,130,116, 2015 | 9 | 2015 |
Effect of Electrical Stress on Josephson Tunneling Characteristics of Junctions D Amparo, SK Tolpygo IEEE transactions on applied superconductivity 19 (3), 154-158, 2009 | 7 | 2009 |
System and method for array diagnostics in superconducting integrated circuit A Inamdar, J Ren, D Amparo US Patent 10,222,416, 2019 | 5 | 2019 |