| Applications of artificial intelligence on the modeling and optimization for analog and mixed-signal circuits: A review M Fayazi, Z Colter, E Afshari, R Dreslinski IEEE Transactions on Circuits and Systems I: Regular Papers 68 (6), 2418-2431, 2021 | 48 | 2021 |
| An open-source framework for autonomous SoC design with analog block generation T Ajayi, S Kamineni, YK Cherivirala, M Fayazi, K Kwon, M Saligane, ... 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020 | 29 | 2020 |
| Tablext: A combined neural network and heuristic based table extractor Z Colter, M Fayazi, Z Benameur-El Youbi, S Kamp, S Yu, R Dreslinski Array 15, 100220, 2022 | 16 | 2022 |
| Versa: A 36-core systolic multiprocessor with dynamically reconfigurable interconnect and memory S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ... IEEE Journal of Solid-State Circuits 57 (4), 986-998, 2022 | 12 | 2022 |
| Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits R Dreslinski, ... GOMACTech, 1111-1116, 2019 | 10 | 2019 |
| AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach M Fayazi, MT Taba, E Afshari, R Dreslinski IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 7 | 2023 |
| A 507 GMACs/J 256-core domain adaptive systolic-array-processor for wireless communication and linear-algebra kernels in 12nm FINFET KY Chen, CS Yang, YH Sun, CW Tseng, M Fayazi, X He, S Feng, Y Yue, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 6 | 2022 |
| Versa: A dataflow-centric multiprocessor with 36 systolic arm cortex-m4f cores and a reconfigurable crossbar-memory hierarchy in 28nm S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 5 | 2021 |
| Fully autonomous mixed signal SoC design & layout generation platform T Ajayi, Y Cherivirala, K Kwon, S Kamineni, M Saligane, M Fayazi, ... IEEE, 2020 | 4 | 2020 |
| A compact CMOS 363 GHz autodyne FMCW radar with 57 GHz bandwidth for dental imaging MT Taba, SMH Naghavi, M Fayazi, A Sadeghi, A Cathelin, E Afshari 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 3 | 2023 |
| FASCINET: A fully automated single-board computer generator using neural networks M Fayazi, Z Colter, Z Benameur-El Youbi, J Bagherzadeh, T Ajayi, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 3 | 2022 |
| FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method M Fayazi, MT Taba, A Tabatabavakili, E Afshari, R Dreslinski 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-8, 2023 | 1 | 2023 |
| Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications S Kamp, M Fayazi, Z Benameur-El, S Yu, R Dreslinski arXiv preprint arXiv:2310.11644, 2023 | 1 | 2023 |
| A Simplified Approach to Two-Port Analysis in Feedback M Fayazi, A Fotowat, Z Kavehvash arXiv preprint arXiv:1908.10274, 2019 | 1 | 2019 |
| Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation T Ajayi, S Kamineni, M Fayazi, YK Cherivirala, K Kwon, S Gupta, W Duan, ... VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on …, 2021 | | 2021 |
| Hot Chips 2020 Posters F Elsabbagh, B Tine, A Chawda, W Gulian, Y Feng, P Roshan, E Lyons, ... 2020 IEEE Hot Chips 32 Symposium (HCS), 1-159, 2020 | | 2020 |
Ronald DreslinskiUniversity of MichiganBestätigte E-Mail-Adresse bei umich.edu
