| RENO: A high-efficient reconfigurable neuromorphic computing accelerator design X Liu, M Mao, B Liu, H Li, Y Chen, B Li, Y Wang, H Jiang, M Barnell, Q Wu, ... Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 121 | 2015 |
| Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators X Liu, M Mao, B Liu, B Li, Y Wang, H Jiang, M Barnell, Q Wu, J Yang, H Li, ... IEEE Transactions on Circuits and Systems I: Regular Papers 63 (5), 617--628, 2016 | 46 | 2016 |
| A heterogeneous computing system with memristor-based neuromorphic accelerators X Liu, M Mao, H Li, Y Chen, H Jiang, JJ Yang, Q Wu, M Barnell High Performance Extreme Computing Conference (HPEC), 2014 IEEE, 1 - 6, 2014 | 24 | 2014 |
| An efficient STT-RAM-based register file in GPU architectures X Liu, M Mao, X Bi, H Li, Y Chen The 20th Asia and South Pacific Design Automation Conference, 490-495, 2015 | 22 | 2015 |
| Neuromorphic computing's yesterday, today, and tomorrow–an evolutional view Y Chen, HH Li, C Wu, C Song, S Li, C Min, HP Cheng, W Wen, X Liu Integration 61, 49-61, 2018 | 20 | 2018 |
| Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems X Liu, W Wen, X Qian, H Li, Y Chen 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 141-146, 2018 | 18 | 2018 |
| STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures X Liu, Y Li, Y Zhang, AK Jones, Y Chen Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific …, 2014 | 13 | 2014 |
| TEMP: thread batch enabled memory partitioning for GPU M Mao, W Wen, X Liu, J Hu, D Wang, Y Chen, H Li the 53rd Annual Design Automation Conference (DAC), 65:1--65:6, 2016 | 10 | 2016 |
| Heterogeneous Systems with Reconfigurable Neuromorphic Computing Accelerators S Li, X Liu, M Mao, H Li, Y Chen, B Li, Y Wang 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 125 - 128, 2016 | 9 | 2016 |
| The applications of memristor devices in next-generation cortical processor designs H Li, B Liu, X Liu, M Mao, Y Chen, Q Wu, Q Qiu 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 17-20, 2015 | 4 | 2015 |
| Neuromorphic hardware acceleration enabled by emerging technologies H Li, X Liu, M Mao, Y Chen, Q Wu, B Mark 2014 International Symposium on Integrated Circuits (ISIC), 2014 | 4 | 2014 |
| Thread batching for high-performance energy-efficient GPU memory design B Li, M Mao, X Liu, T Liu, Z Liu, W Wen, Y Chen, H Li ACM Journal on Emerging Technologies in Computing Systems (JETC) 15 (4), 1-21, 2019 | 1 | 2019 |
| Emerging memristor technology enabled next generation cortical processor H Li, M Hu, X Liu, M Mao, C Li, S Duan 2014 27th IEEE International System-on-Chip Conference (SOCC), 377-382, 2014 | 1 | 2014 |
| Exploring Applications of STT-RAM in GPU Architectures X Liu, M Mao, X Bi, H Li, Y Chen IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 | | 2020 |
| Applications of Emerging Memory in Modern Computer Systems: Storage and Acceleration X Liu University of Pittsburgh, 2017 | | 2017 |
| Hardware acceleration for neuromorphic computing: An evolving view B Liu, X Liu, C Liu, W Wen, M Meng, H Li, Y Chen 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015 | | 2015 |
Yiran ChenProfessor, Electrical and Computer Engineering, Duke UniversityBestätigte E-Mail-Adresse bei duke.edu
