Fast-SL: An efficient algorithm to identify synthetic lethal sets in metabolic networks A Pratapa, S Balachandran, K Raman
Bioinformatics, 2015
61 2015 A-priori wirelength and interconnect estimation based on circuit characteristics S Balachandran, D Bhatia
Proceedings of the 2003 international workshop on System-level interconnect …, 2003
46 2003 On metrics for comparing routability estimation methods for FPGAs P Kannan, S Balachandran, D Bhatia
Proceedings of the 39th annual Design Automation Conference, 70-75, 2002
37 2002 The Implications of Shared Data Synchronization Techniques on Multi-core Energy Efficiency AJ Gautham, K Korgaonkar, S Pathanjali, S Balachandran, V Kamakoti
Proceedings of the 2012 USENIX conference on Power-Aware Computing and …, 2012
34 2012 fGREP-fast generic routing demand estimation for placed FPGA circuits P Kannan, S Balachandran, D Bhatia
Field-Programmable Logic and Applications: 11th International Conference …, 2001
29 2001 A new parallel algorithm for minimum spanning tree problem R Setia, A Nedunchezhian, S Balachandran
Proc. International Conference on High Performance Computing (HiPC), 1-5, 2009
21 2009 REDUCT: Keep it close, keep it cool!: Efficient scaling of DNN inference on multi-core CPUs with near-cache compute AV Nori, R Bera, S Balachandran, J Rakshit, OJ Omer, A Abuhatzera, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
18 2021 Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction R Bera, K Kanellopoulos, S Balachandran, D Novo, A Olgun, ...
55th IEEE/ACM International Symposium on Microarchitecture, 2022
17 2022 Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers B Panda, S Balachandran
Computer Architecture Letters, DOI: 10.1109/LCA.2015.2428703, 2015
16 2015 On metrics for comparing interconnect estimation methods for FPGAs P Kannan, S Balachandran, D Bhatia
IEEE transactions on very large scale integration (VLSI) systems 12 (4), 381-385, 2004
16 2004 : Cost Based Hardware Optimization for Asymmetric Multicore ProcessorsJKV Sreelatha, S Balachandran, R Nasre
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 163-176, 2018
12 2018 A new wirelength model for analytical placement BNB Ray, S Balachandran
2011 IEEE Computer Society Annual Symposium on VLSI, 90-95, 2011
12 2011 CAFFEINE: A utility-driven prefetcher aggressiveness engine for multicores B Panda, S Balachandran
ACM Transactions on Architecture and Code Optimization (TACO) 12 (3), 1-25, 2015
11 2015 Set-cover heuristics for two-level logic minimization A Kagliwal, S Balachandran
2012 25th International Conference on VLSI Design, 197-202, 2012
11 2012 Application behavior aware re-reference interval prediction for shared LLC P Lathigara, S Balachandran, V Singh
2015 33rd IEEE International Conference on Computer Design (ICCD), 172-179, 2015
10 2015 Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control B Panda, S Balachandran
DATE 2014, 2014
9 2014 Hardware prefetchers for emerging parallel applications B Panda, S Balachandran
Proceedings of the 21st international conference on Parallel architectures …, 2012
9 2012 CUPL: A compile-time uncoalesced memory access pattern locator for CUDA M Amilkanthwar, S Balachandran
Proceedings of the 27th international ACM conference on International …, 2013
8 2013 On routing demand and congestion estimation for FPGAs S Balachandran, P Kannan, D Bhatia
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002
8 2002 ProWATCh: A Proactive Cross-Layer Workload Aware Temperature Management Framework for Low-Power Chip Multi-Processors M Patnaik
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2015
7 2015