| FPGA design of a fast 32-bit floating point multiplier unit A Jain, B Dash, AK Panda, M Suresh 2012 International Conference on Devices, Circuits and Systems (ICDCS), 545-547, 2012 | 31 | 2012 |
| Design of arithmetic circuits using reversible logic gates and power dissipation calculation M Mahapatro, SK Panda, J Satpathy, M Saheel, M Suresh, AK Panda, ... 2010 international symposium on electronic system design, 85-90, 2010 | 29 | 2010 |
| Low power aware standard cells using dual rail multi threshold null convention logic methodology M Suresh, AK Panda, J Sudhakar Microprocessors and Microsystems 68, 28-33, 2019 | 7 | 2019 |
| Simplistic approach to reduce thermal issues in 3D IC integration technology B Rakesh, D Prasad, CU Kumari, NA Vighnesh, M Suresh, AK Panigrahy Materials Today: Proceedings 45, 1399-1402, 2021 | 5 | 2021 |
| A Novel Flash Analog-to-Digital Converter Design Using Cadence Tool M Suresh, K Sadangi, S Sahu, AK Panda 2009 International Conference on Advances in Recent Technologies in …, 2009 | 4 | 2009 |
| An Analysis of MCML 8-bit multiplier for high speed application E Pattanaik, AK Panda, M Suresh international Journal of VLSI and Embedded Systems 4 (1), 2013 | 3 | 2013 |
| Analysis of CMOS And MTCMOS Circuits Using 250 Nano Meter Technology M Suresh, AK Panda, M Sukla, MP Vasanthi, S Santhi CS & IT-CSCP, 41-51, 2016 | 2 | 2016 |
| Power-Delay Efficient Asynchronous Design Approach Using Galeor M Suresh, J Sudhakar, AK Panda International Journal of Advanced Research in Engineering and Technology 10 (1), 2019 | | 2019 |
Ajit Kumar PandaElectronics Center of ExcellenceBestätigte E-Mail-Adresse bei ieee.org
