Jean-Pierre Raskin
Jean-Pierre Raskin
Université catholique de Louvain, Engineering School of Louvain
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Zitiert von
Zitiert von
Substrate crosstalk reduction using SOI technology
JP Raskin, A Viviani, D Flandre, JP Colinge
IEEE Transactions on Electron Devices 44 (12), 2252-2261, 1997
Influence of device engineering on the analog and RF performances of SOI MOSFETs
V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ...
IEEE Transactions on Electron Devices 50 (3), 577-588, 2003
New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity
D Lederer, JP Raskin
IEEE Electron Device Letters 26 (11), 805-807, 2005
Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs
G Larrieu, E Dubois, R Valentin, N Breil, F Danneville, G Dambrine, ...
2007 IEEE International Electron Devices Meeting, 147-150, 2007
Arsenic-segregated rare-earth silicide junctions: reduction of Schottky barrier and integration in metallic n-MOSFETs on SOI
G Larrieu, DA Yarekha, E Dubois, N Breil, O Faynot
IEEE Electron Device Letters 30 (12), 1266-1268, 2009
Fabrication method of so1 semiconductor devices
D Fladre, A De Mevergnies, JP Raskins
US Patent App. 10/471,847, 2004
A 94-GHz aperture-coupled micromachined microstrip antenna
GP Gauthier, JP Raskin, LPB Katehi, GM Rebeiz
IEEE Transactions on Antennas and Propagation 47 (12), 1761-1766, 1999
Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling
JP Raskin, R Gillon, J Chen, D Vanhoenacker-Janvier, JP Colinge
IEEE Transactions on Electron Devices 45 (5), 1017-1025, 1998
Low-temperature wafer bonding: A study of void formation and influence on bonding strength
XX Zhang, JP Raskin
Journal of microelectromechanical systems 14 (2), 368-382, 2005
Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer
DC Kerr, JM Gering, TG McKay, MS Carroll, CR Neve, JP Raskin
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008
Comparison of TiSi2, CoSi2, and NiSi for thin‐film silicon‐on‐insulator applications
J Chen, JP Colinge, D Flandre, R Gillon, JP Raskin, D Vanhoenacker
Journal of the Electrochemical Society 144 (7), 2437, 1997
Substrate loss mechanisms for microstrip and CPW transmission lines on lossy silicon wafers
D Lederer, JP Raskin
Solid-State Electronics 47 (11), 1927-1936, 2003
Micromachined thin-film sensors for SOI-CMOS co-integration
J Laconte, D Flandre, JP Raskin
Springer Science & Business Media, 2006
What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?
G Dambrine, C Raynaud, D Lederer, M Dehan, O Rozeaux, ...
IEEE Electron Device Letters 24 (3), 189-191, 2003
Semiconductor-on-insulator materials for nanoelectronics applications
A Nazarov, JP Colinge, F Balestra, JP Raskin, F Gamiz, VS Lysenko
Springer, 2011
Raman and XPS characterization of vanadium oxide thin films with temperature
F Ureña-Begara, A Crunteanu, JP Raskin
Applied Surface Science 403, 717-727, 2017
FinFET analogue characterization from DC to 110 GHz
D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ...
Solid-State Electronics 49 (9), 1488-1496, 2005
New on-chip nanomechanical testing laboratory-applications to aluminum and polysilicon thin films
S Gravier, M Coulombier, A Safi, N André, A Boé, JP Raskin, T Pardoen
Journal of microelectromechanical systems 18 (3), 555-569, 2009
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
JP Raskin, TM Chung, V Kilchytska, D Lederer, D Flandre
IEEE Transactions on Electron Devices 53 (5), 1088-1095, 2006
Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications
A Kranti, TM Chung, D Flandre, JP Raskin
Solid-State Electronics 48 (6), 947-959, 2004
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