| IP core steganography for protecting DSP kernels used in CE systems A Sengupta, M Rathor IEEE Transactions on Consumer Electronics 65 (4), 506-515, 2019 | 39 | 2019 |
| IP core steganography using switch based key-driven hash-chaining and encoding for securing DSP kernels used in CE systems M Rathor, A Sengupta IEEE Transactions on Consumer Electronics 66 (3), 251-260, 2020 | 26 | 2020 |
| Securing hardware accelerators for CE systems using biometric fingerprinting A Sengupta, M Rathor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (9 …, 2020 | 24 | 2020 |
| Structural obfuscation and crypto-steganography-based secured JPEG compression hardware for medical imaging systems A Sengupta, M Rathor IEEE Access 8, 6543-6565, 2020 | 22 | 2020 |
| Enhanced security of DSP circuits using multi-key based structural obfuscation and physical-level watermarking for consumer electronics systems A Sengupta, M Rathor IEEE Transactions on Consumer Electronics 66 (2), 163-172, 2020 | 21 | 2020 |
| Facial biometric for securing hardware accelerators A Sengupta, M Rathor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 112-123, 2020 | 16 | 2020 |
| Crypto-based dual-phase hardware steganography for securing IP cores A Sengupta, M Rathor IEEE Letters of the Computer Society 2 (4), 32-35, 2019 | 15 | 2019 |
| Protecting DSP kernels using robust hologram-based obfuscation A Sengupta, M Rathor IEEE Transactions on Consumer Electronics 65 (1), 99-108, 2018 | 12 | 2018 |
| Obfuscated hardware accelerators for image processing filters—Application specific and functionally reconfigurable processors A Sengupta, M Rathor IEEE Transactions on Consumer Electronics 66 (4), 386-395, 2020 | 8 | 2020 |
| Security of functionally obfuscated DSP core against removal attack using SHA-512 based key encryption hardware A Sengupta, M Rathor IEEE Access 7, 4598-4610, 2018 | 8 | 2018 |
| Exploring handwritten signature image features for hardware security M Rathor, A Sengupta, R Chaurasia, A Anshul IEEE Transactions on Dependable and Secure Computing, 2022 | 4 | 2022 |
| Securing hardware accelerators using multi-key based structural obfuscation A Sengupta, M Rathor, S Patil, NG Harishchandra IEEE Letters of the Computer Society 3 (1), 21-24, 2020 | 4 | 2020 |
| Design flow of secured N-point DFT application specific processor using obfuscation and steganography M Rathor, A Sengupta IEEE Letters of the Computer Society 3 (1), 13-16, 2020 | 4 | 2020 |
| Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores M Rathor, A Anshul, K Bharath, R Chaurasia, A Sengupta Computers and Electrical Engineering 105, 108476, 2023 | 3 | 2023 |
| Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography M Rathor, P Sarkar, VK Mishra, A Sengupta 2020 IEEE 10th International Conference on Consumer Electronics (ICCE-Berlin …, 2020 | 3 | 2020 |
| HLS based IP protection of reusable cores using biometric fingerprint A Sengupta, M Rathor IEEE Letters of the Computer Society 3 (2), 42-45, 2020 | 3 | 2020 |
| Robust logic locking for securing reusable DSP cores M Rathor, A Sengupta IEEE Access 7, 120052-120064, 2019 | 2 | 2019 |
| Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature M Rathor, GP Rathor IEEE Design & Test, 2023 | 1 | 2023 |
| Signature biometric based authentication of IP cores for secure electronic systems M Rathor, A Sengupta 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 384-388, 2021 | 1 | 2021 |
| Hardware (IP) watermarking during behavioral synthesis A Sengupta, M Rathor Behavioral Synthesis for Hardware Security, 119-145, 2021 | 1 | 2021 |
Prof. Anirban Sengupta, Fellow IET, Fe...Full Professor, CSE, Indian Institute of Technology (IIT) IndoreBestätigte E-Mail-Adresse bei iiti.ac.in
