| REDO-random excitation and deterministic observation-first commercial experiment MR Grimaila, S Lee, J Dworak, KM Butler, B Stewart, H Balachandran, ... Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 268-274, 1999 | 146 | 1999 |
| Don't forget to lock your SIB: hiding instruments using P1687 J Dworak, A Crouch, J Potter, A Zygmontowicz, M Thornton 2013 IEEE International Test Conference (ITC), 1-10, 2013 | 99 | 2013 |
| Defect-oriented testing and defective-part-level prediction J Dworak, JD Wicker, S Lee, MR Grimaila, MR Mercer, KM Butler, ... IEEE Design & Test of Computers 18 (1), 31-41, 2001 | 74 | 2001 |
| Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network A Zygmontowicz, J Dworak, A Crouch, J Potter 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 62 | 2014 |
| A new ATPG algorithm to limit test set size and achieve multiple detections of all faults S Lee, B Cobb, J Dworak, MR Grimaila, MR Mercer Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 59 | 2002 |
| Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D J Dworak, MR Grimaila, S Lee, LC Wang, MR Mercer Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 48 | 2000 |
| Using implications for online error detection K Nepal, N Alves, J Dworak, RI Bahar 2008 IEEE International Test Conference, 1-10, 2008 | 45 | 2008 |
| A cost effective approach for online error detection using invariant relationships N Alves, A Buben, K Nepal, J Dworak, RI Bahar IEEE Transactions on computer-aided design of Integrated Circuits and …, 2010 | 40 | 2010 |
| Enhancing test efficiency for delay fault testing using multiple-clocked schemes JJ Liou, LC Wang, KT Cheng, J Dworak, MR Mercer, R Kapur, ... Proceedings of the 39th annual Design Automation Conference, 371-374, 2002 | 38 | 2002 |
| A call to action: Securing IEEE 1687 and the need for an IEEE test security standard J Dworak, A Crouch 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-4, 2015 | 37 | 2015 |
| Echeloned IJTAG data protection S Kan, J Dworak, JG Dunham 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1-6, 2016 | 35 | 2016 |
| Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture F Zhang, D Hwong, Y Sun, A Garcia, S Alhelaly, G Shofner, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 33 | 2016 |
| Increasing IJTAG bandwidth and managing security through parallel locking-SIBs S Gupta, A Crouch, J Dworak, D Engels 2017 IEEE International Test Conference (ITC), 1-10, 2017 | 30 | 2017 |
| Board security enhancement using new locking SIB-based architectures J Dworak, Z Conroy, A Crouch, J Potter 2014 International Test Conference, 1-10, 2014 | 29 | 2014 |
| Enhancing online error detection through area-efficient multi-site implications N Alves, Y Shi, J Dworak, RI Bahar, K Nepal 29th VLSI Test Symposium, 241-246, 2011 | 20 | 2011 |
| Balanced excitation and its effect on the fortuitous detection of dynamic defects J Dworak, B Cobb, J Wingfield, MR Mercer Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 19 | 2004 |
| Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies J Dworak, MR Grimaila, S Lee, LC Wang, MR Mercer International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999 | 19 | 1999 |
| Mitigating simple power analysis attacks on LSIB key logic S Gupta, J Dworak, D Engels, A Crouch 2017 IEEE North Atlantic Test Workshop (NATW), 1-6, 2017 | 18 | 2017 |
| Analysis of delay test effectiveness with a multiple-clock scheme JJ Liou, LC Wang, KT Cheng, J Dworak, MR Mercer, R Kapur, ... Proceedings. International Test Conference, 407-416, 2002 | 16 | 2002 |
| On reducing scan shift activity at RTL E Alpaslan, Y Huang, X Lin, WT Cheng, J Dworak IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 15 | 2010 |
