Andreas Zankl
Andreas Zankl
Security Researcher, Fraunhofer AISEC
Bestätigte E-Mail-Adresse bei aisec.fraunhofer.de
TitelZitiert vonJahr
AutoLock: Why Cache Attacks on {ARM} Are Harder Than You Think
M Green, L Rodrigues-Lima, A Zankl, G Irazoqui, J Heyszl, T Eisenbarth
26th {USENIX} Security Symposium ({USENIX} Security 17), 1075-1091, 2017
172017
PerfWeb: How to violate web privacy with hardware performance events
B Gulmezoglu, A Zankl, T Eisenbarth, B Sunar
European Symposium on Research in Computer Security, 80-97, 2017
132017
DATA – Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries
S Weiser, A Zankl, R Spreitzer, K Miller, S Mangard, G Sigl
27th USENIX Security Symposium (USENIX Security 18), 2018
102018
How to break secure boot on fpga socs through malicious hardware
N Jacob, J Heyszl, A Zankl, C Rolfes, G Sigl
International Conference on Cryptographic Hardware and Embedded Systems, 425-442, 2017
102017
Exploiting bus communication to improve cache attacks on systems-on-chips
J Sepulveda, M Gross, A Zankl, G Sigl
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 284-289, 2017
92017
Automated detection of instruction cache leaks in modular exponentiation software
A Zankl, J Heyszl, G Sigl
International Conference on Smart Card Research and Advanced Applications …, 2016
82016
Towards protected mpsoc communication for information protection against a malicious noc
J Sepúlveda, A Zankl, D Flórez, G Sigl
Procedia computer science 108, 1103-1112, 2017
72017
Earthquake—A NoC-based optimized differential cache-collision attack for MPSoCs
C Reinbrecht, B Forlin, A Zankl, J Sepúlveda
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 648-653, 2018
52018
Towards efficient evaluation of a time-driven cache attack on modern processors
A Zankl, K Miller, J Heyszl, G Sigl
European Symposium on Research in Computer Security, 3-19, 2016
52016
Minimizing the costs of side-channel analysis resistance evaluations in early design steps
T Korak, T Plos, A Zankl
2013 International Conference on Availability, Reliability and Security, 169-177, 2013
42013
Side-channel attacks in the Internet of Things: Threats and challenges
A Zankl, H Seuschek, G Irazoqui, B Gulmezoglu
Solutions for Cyber-Physical Systems Ubiquity, 325-357, 2018
32018
Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT
J Sepulveda, A Zankl, O Mischke
2017 30th IEEE International System-on-Chip Conference (SOCC), 120-125, 2017
22017
Compromising FPGA SoCs using malicious hardware blocks
N Jacob, C Rolfes, A Zankl, J Heyszl, G Sigl
Proceedings of the Conference on Design, Automation & Test in Europe, 1122-1127, 2017
22017
Undermining user privacy on mobile devices using ai
B Gulmezoglu, A Zankl, MC Tol, S Islam, T Eisenbarth, B Sunar
Proceedings of the 2019 ACM Asia Conference on Computer and Communications …, 2019
12019
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC
M Gross, N Jacob, A Zankl, G Sigl
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware …, 2019
2019
EGIS NoC: A secure-enhanced interconnection to prevent Architectural Channel Attacks
C Reinbrecht, B Forlin, A Zankl, J Sepulveda
Testmethoden und Zuverlässigkeit von Schaltungen und Systemen,{TUZ} 2018, 2018
2018
Earthquake-A NoC-based optimized differential collision cache attack for MPSoCs
C Reinbrecht, B Forlin, A Zankl, J Sepulveda
Design, Automation & Test in Europe,{DATE} 2018, 2018
2018
DATA-Differential Address Trace Analysis
S Weiser, A Zankl, R Spreitzer, K Miller, S Mangard, G Sigl
crypto day matters 28, 2018
2018
How to Break Secure Boot on FPGA SoCs Through Malicious Hardware
A Zankl, C Rolfes, G Sigl
Cryptographic Hardware and Embedded Systems–CHES 2017: 19th International …, 2017
2017
Towards trace-driven cache attacks on Systems-on-Chips—exploiting bus communication
J Sepulveda, M Gross, A Zankl, G Sigl
2017 12th International Symposium on Reconfigurable Communication-centric …, 2017
2017
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