Sapan Agarwal
Sapan Agarwal
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Zitiert von
Zitiert von
A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing
Y van de Burgt, E Lubberman, EJ Fuller, ST Keene, GC Faria, S Agarwal, ...
Nature materials 16 (4), 414-418, 2017
Li‐ion synaptic transistor for low power analog computing
EJ Fuller, FE Gabaly, F Léonard, S Agarwal, SJ Plimpton, ...
Advanced Materials 29 (4), 1604310, 2017
Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing
EJ Fuller, ST Keene, A Melianas, Z Wang, S Agarwal, Y Li, Y Tuchman, ...
Science 364 (6440), 570-574, 2019
Tunnel field effect transistor with raised germanium source
SH Kim, S Agarwal, ZA Jacobson, P Matheu, C Hu, TJK Liu
IEEE electron device letters 31 (10), 1107-1109, 2010
Resistive memory device requirements for a neural algorithm accelerator
S Agarwal, SJ Plimpton, DR Hughart, AH Hsia, I Richter, JA Cox, ...
2016 International Joint Conference on Neural Networks (IJCNN), 929-938, 2016
Band-edge steepness obtained from Esaki/backward diode current–voltage characteristics
S Agarwal, E Yablonovitch
IEEE Transactions on Electron Devices 61 (5), 1488-1493, 2014
Energy scaling advantages of resistive memory crossbar based computation and its application to sparse coding
S Agarwal, TT Quach, O Parekh, AH Hsia, EP DeBenedictis, CD James, ...
Frontiers in neuroscience 9, 484, 2016
Multiscale co-design analysis of energy, latency, area, and accuracy of a ReRAM analog neural training accelerator
MJ Marinella, S Agarwal, A Hsia, I Richter, R Jacobs-Gedrim, J Niroula, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1 …, 2018
Engineering the electron–hole bilayer tunneling field-effect transistor
S Agarwal, JT Teherani, JL Hoyt, DA Antoniadis, E Yablonovitch
IEEE Transactions on Electron Devices 61 (5), 1599-1606, 2014
Designing a low voltage, high current tunneling transistor
S Agarwal, E Yablonovitch, TJK Liu, KJ Kuhn
CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, 79-116, 2015
Impact of quantization energy and gate leakage in bilayer tunneling transistors
JT Teherani, S Agarwal, E Yablonovitch, JL Hoyt, DA Antoniadis
IEEE Electron Device Letters 34 (2), 298-300, 2013
Achieving ideal accuracies in analog neuromorphic computing using periodic carry
S Agarwal, RBJ Gedrim, AH Hsia, DR Hughart, EJ Fuller, AA Talin, ...
2017 Symposium on VLSI Technology, T174-T175, 2017
Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on
S Agarwal, E Yablonovitch
69th Device Research Conference, 199-200, 2011
Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors
Y Li, EJ Fuller, S Asapu, S Agarwal, T Kurita, JJ Yang, AA Talin
ACS applied materials & interfaces 11 (42), 38982-38992, 2019
Neuromemristive systems: boosting efficiency through brain-inspired computing
C Merkel, R Hasan, N Soures, D Kudithipudi, T Taha, S Agarwal, ...
Computer 49 (10), 56-64, 2016
Auger generation as an intrinsic limit to tunneling field-effect transistor performance
JT Teherani, S Agarwal, W Chern, PM Solomon, E Yablonovitch, ...
Journal of Applied Physics 120 (8), 084507, 2016
Using floating-gate memory to train ideal accuracy neural networks
S Agarwal, D Garland, J Niroula, RB Jacobs-Gedrim, A Hsia, ...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …, 2019
Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks
AM Zyarah, N Soures, L Hays, RB Jacobs-Gedrim, S Agarwal, ...
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
Impact of linearity and write noise of analog resistive memory devices in a neural algorithm accelerator
RB Jacobs-Gedrim, S Agarwal, KE Knisely, JE Stevens, ...
2017 IEEE International Conference on Rebooting Computing (ICRC), 1-10, 2017
Pronounced effect of pn-junction dimensionality on tunnel switch threshold shape
S Agarwal, E Yablonovitch
arXiv preprint arXiv:1109.0096, 2011
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