Emre Ozer
Emre Ozer
Arm Research
Bestätigte E-Mail-Adresse bei arm.com
TitelZitiert vonJahr
Managing cache coherency in a data processing apparatus
E Özer, SD Biles, SA Ford
US Patent 7,937,535, 2011
Scale-out processors
P Lotfi-Kamran, B Grot, M Ferdman, S Volos, O Kocberber, J Picorel, ...
ACM SIGARCH Computer Architecture News 40 (3), 500-511, 2012
Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures
E Ozer, S Banerjia, TM Conte
Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998
Multiple thread instruction fetch from different cache levels
E Özer, SD Biles
US Patent 7,769,955, 2010
Contention management for a hardware transactional memory
G Blake, TN Mudge, SD Biles, NYS Chong, E Ozer, RG Dreslinski
US Patent App. 12/292,565, 2009
Cache miss detection in a data processing apparatus
M Ghosh, E Özer, SD Biles
US Patent 8,099,556, 2012
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
M Ghosh, E Ozer, S Ford, S Biles, HHS Lee
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
The HiPEAC Vision 2019
M Duranton, K De Bosschere, B Coppens, C Gamrat, M Gray, H Munk, ...
Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction
YP Raykov, E Ozer, G Dasika, A Boukouvalas, MA Little
Proceedings of the 2016 ACM International Joint Conference on Pervasive and …, 2016
Weld: A multithreading technique towards latency-tolerant VLIW processors
E Özer, TM Conte, S Sharma
International Conference on High-Performance Computing, 192-203, 2001
Processor and System-on-chip Simulation
R Leupers, O Temam
Springer, 2010
Multiple-valued logic buses for reducing bus energy in low-power systems
E Özer, R Sendag, D Gregg
IEE Proceedings-Computers and Digital Techniques 153 (4), 270-282, 2006
A stochastic bitwidth estimation technique for compact and low-power custom processors
E Özer, AP Nisbet, D Gregg
ACM Transactions on Embedded Computing Systems (TECS) 7 (3), 1-30, 2008
Stochastic bit-width approximation using extreme value theory for customizable processors
E Özer, AP Nisbet, D Gregg
International Conference on Compiler Construction, 250-264, 2004
Data processing apparatus and method for managing multiple program threads executed by processing circuitry
E Özer, SD Biles
US Patent 8,205,206, 2012
An analytical framework for estimating tco and exploring data center design space
D Hardy, M Kleanthous, I Sideris, AG Saidi, E Ozer, Y Sazeides
2013 IEEE International Symposium on Performance Analysis of Systems and …, 2013
Instruction issue control within a multi-threaded in-order superscalar processor
E Özer, V Vasekin, SD Biles
US Patent 7,707,390, 2010
Modulation of CGG triplet repeat binding protein 1 expression
C Bennett, N Dean, K Dobie
US Patent App. 10/303,566, 2004
High-performance and low-cost dual-thread VLIW processor using Weld architecture paradigm
E Ozer, TM Conte
IEEE Transactions on Parallel and Distributed Systems 16 (12), 1132-1142, 2005
A fast interrupt handling scheme for VLIW processors
E Ozer, SW Sathaye, KN Menezes, S Banerjia, MD Jennings, TM Conte
Proceedings. 1998 International Conference on Parallel Architectures and …, 1998
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