Nam Sung Kim
Nam Sung Kim
W.J. ‘Jerry’ Sanders III – AMD, Inc. Endowed Chair Professor and Fellow of ACM/IEEE
Bestätigte E-Mail-Adresse bei - Startseite
Zitiert von
Zitiert von
Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
Leakage current: Moore's law meets static power
NS Kim, T Austin, D Blaauw, T Mudge, JS Hu, MJ Irwin, M Kandemir, ...
computer, 68-75, 2003
Drowsy caches: simple techniques for reducing leakage power
K Flautner, NS Kim, S Martin, D Blaauw, T Mudge
ACM SIGARCH Computer architecture news 30 (2), 148-157, 2002
GPUWattch: Enabling energy optimizations in GPGPUs
J Leng, T Hetherington, A ElTantawy, S Gilani, NS Kim, TM Aamodt, ...
International Symposium on Computer Architecture, 487-498, 2013
Approximate computing: A survey
Q Xu, T Mytkowicz, NS Kim
IEEE Design & Test 33 (1), 8-22, 2015
Razor: circuit-level correction of timing errors for low-power operation
D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner
IEEE Micro 24 (6), 10-20, 2004
Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance
KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ...
IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
A Farmahini-Farahani, JH Ahn, K Morrow, NS Kim
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
Energy-efficient approximate multiplication for digital signal processing and classification applications
S Narayanamoorthy, HA Moghaddam, Z Liu, T Park, NS Kim
IEEE transactions on very large scale integration (VLSI) systems 23 (6 …, 2014
Circuit and microarchitectural techniques for reducing cache leakage power
NS Kim, K Flautner, D Blaauw, T Mudge
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 167-184, 2004
The case for GPGPU spatial multitasking
JT Adriaens, K Compton, NS Kim, MJ Schulte
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
Drowsy instruction caches. leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
NS Kim, K Flautner, D Blaauw, T Mudge
35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002
Yield-driven near-threshold SRAM design
G Chen, D Sylvester, D Blaauw, T Mudge, NS Kim
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007
Hardware architecture and software stack for PIM based on commercial DRAM technology: Industrial product
S Lee, S Kang, J Lee, H Kim, E Lee, S Seo, H Yoon, S Lee, K Lim, H Shin, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems
H Asghari-Moghaddam, YH Son, JH Ahn, NS Kim
2016 49th annual IEEE/ACM international symposium on Microarchitecture …, 2016
25.4 a 20nm 6gb function-in-memory dram, based on hbm2 with a 1.2 tflops programmable computing unit using bank-level parallelism, for machine learning applications
YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021
Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs
M Khellah, Y Ye, N Kim, D Somasekhar, G Pandya, A Farhang, K Zhang, ...
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 9-10, 2006
Pipe-SGD: A decentralized pipelined SGD framework for distributed deep net training
Y Li, M Yu, S Li, S Avestimehr, NS Kim, A Schwing
Advances in Neural Information Processing Systems 31, 2018
VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages
UR Karpuzcu, KB Kolluru, NS Kim, J Torrellas
IEEE/IFIP International Conference on Dependable Systems and Networks (DSN …, 2012
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