| 1.25 GS/S 12bit and 2.27 mW digital to analog converter (DAC) with 70.22 SNDR based on new hybrid RC procedure in 180nm CMOS S Mahdavi, M Poreh, L Alizadeh, B Moradkhani, R Ebrahimi International Journal of Microelectronics and Computer Science 8 (4), 2017 | 6 | 2017 |
| A new approach to optimize the defuzzification unit of fuzzy systems B Moradkhani, MS Dilmaghani, AB Rezaeii 2019 27th Iranian Conference on Electrical Engineering (ICEE), 274-279, 2019 | 2 | 2019 |
| Merging DAC and fuzzifier structures as a new approach in membership function generation B Moradkhani, AB Rezaeii, MS Dilmaghani Electrical Engineering (ICEE), Iranian Conference on, 269-272, 2018 | 2 | 2018 |
| A− 38 to 57dB 26.6 MHz 1.96 mW with 73.22 dB SNDR variable gain amplifier in 0.18 μm CMOS S Mahdavi, B Moradkhani, F Noruzpur 2017 IEEE International Conference on Power, Control, Signals and …, 2017 | 2 | 2017 |
| A 41MHz 63dB and 1.22mW Variable Gain Amplifier in 0.xn--18m-yyc CMOS S Mahdavi, F Raheli, B Moradkhani, A Soltani 3rd International Conference on Knowledge-Based Engineering and Innovation …, 2016 | | 2016 |
Mehdi Sefidgar DilmaghaniPhD Student at University of GalwayVerified email at nuigalway.ie
Mehdi Sefidgar DilmaghaniPhD Student at University of GalwayVerified email at nuigalway.ie