| Methods for improving transition delay fault coverage using broadside tests N Devtaprasanna, A Gunda, P Krishnamurthy, SM Reddy, I Pomeranz Test Conference, 2005. Proceedings. ITC 2005. IEEE International, 10 pp.-265, 2005 | 63 | 2005 |
| Effective and efficient test pattern generation for small delay defect SK Goel, N Devta-Prasanna, RP Turakhia 2009 27th IEEE VLSI Test Symposium, 111-116, 2009 | 62 | 2009 |
| On the detectability of scan chain internal faults an industrial case study F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 26th IEEE VLSI Test Symposium (vts 2008), 79-84, 2008 | 57 | 2008 |
| A unified method to detect transistor stuck-open faults and transition delay faults N Devtaprasanna, A Gunda, P Krishnamurthy, SM Reddy, I Pomeranz Test Symposium, 2006. ETS'06. Eleventh IEEE European, 185-192, 2006 | 36 | 2006 |
| Scan test cost and power reduction through systematic scan reconfiguration A Al-Yamani, N Devta-Prasanna, E Chmelar, M Grinchuk, A Gunda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 30 | 2007 |
| Detection of internal stuck-open faults in scan chains F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2008 IEEE International Test Conference, 1-10, 2008 | 29 | 2008 |
| A novel method of improving transition delay fault coverage using multiple scan enable signals N Devtaprasanna, A Gunda, P Krishnamurthy, SM Reddy, I Pomeranz Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005 | 25 | 2005 |
| Accurate measurement of small delay defect coverage of test patterns N Devta-Prasanna, SK Goel, A Gunda, M Ward, P Krishnamurthy 2009 International Test Conference, 1-10, 2009 | 24 | 2009 |
| Method for implementing test generation for systematic scan reconfiguration in an integrated circuit AA Alvamani, N Devta-Prasanna, A Gunda US Patent 7,555,688, 2009 | 22 | 2009 |
| Test generation for open defects in cmos circuits N Devtaprasanna, A Gunda, P Krishnamurthy, SM Reddy, I Pomeranz Defect and Fault Tolerance in VLSI Systems, 2006. DFT'06. 21st IEEE …, 2006 | 22 | 2006 |
| Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study SK Goel, N Devta-Prasanna, M Ward 2009 International Test Conference, 1-10, 2009 | 21 | 2009 |
| Improving the detectability of resistive open faults in scan cells F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009 | 21 | 2009 |
| Improved delay fault coverage using subsets of flip-flops to launch transitions N Devtaprasanna, A Gunda, P Krishnamurthy, SM Reddy, I Pomeranz Test Symposium, 2005. Proceedings. 14th Asian, 202-207, 2005 | 16 | 2005 |
| Silicon evaluation of faster than at-speed transition delay tests S Chakravarty, N Devta-Prasanna, A Gunda, J Ma, F Yang, H Guo, R Lai, ... 2012 IEEE 30th VLSI Test Symposium (VTS), 80-85, 2012 | 14 | 2012 |
| System and device for reducing instantaneous voltage droop during a scan shift operation N Devta-Prasanna, SK Goel, AK Gunda US Patent 8,627,160, 2014 | 13 | 2014 |
| Detectability of internal bridging faults in scan chains F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2009 Asia and South Pacific Design Automation Conference, 678-683, 2009 | 12 | 2009 |
| Design-for-test technique to reduce test volume including a clock gate controller NB Devta-Prasanna US Patent 8,412,994, 2013 | 10 | 2013 |
| System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop A Gunda, N Devta-Prasanna US Patent 7,461,307, 2008 | 9 | 2008 |
| Method and system for improving quality of a circuit through non-functional test pattern identification A Gunda, N Devta-Prasanna US Patent 7,461,315, 2008 | 7 | 2008 |
| Detection of transistor stuck-open faults in asynchronous inputs of scan cells F Yang, S Chakravarty, N Devta-Prasanna, SM Reddy, I Pomeranz 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 7 | 2008 |
Sudhakar ReddyDepartment of ECE, University of IowaBestätigte E-Mail-Adresse bei engineering.uiowa.edu
