GeniusRoute: A new analog routing paradigm using generative neural network guidance K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
82 2019 MAGICAL: Toward fully automated analog IC layout leveraging human and machine intelligence B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
81 2019 Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
78 2019 A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- W Zhao, S Li, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 55 (3), 666-679, 2019
66 2019 MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII H Chen, M Liu, B Xu, K Zhu, X Tang, S Li, Y Lin, N Sun, DZ Pan
IEEE Design & Test 38 (2), 19-26, 2020
60 2020 S3 DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity M Liu, W Li, K Zhu, B Xu, Y Lin, L Shen, X Tang, N Sun, DZ Pan
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 193-198, 2020
47 2020 Hardware-software co-design of slimmed optical neural networks Z Zhao, D Liu, M Li, Z Ying, L Zhang, B Xu, B Yu, RT Chen, DZ Pan
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
47 2019 A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology B Xu, S Li, N Sun, DZ Pan
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
38 2017 Hierarchical and analytical placement techniques for high-performance analog circuits B Xu, S Li, X Xu, N Sun, DZ Pan
Proceedings of the 2017 ACM on International Symposium on Physical Design, 55-62, 2017
36 2017 Device layer-aware analytical placement for analog circuits B Xu, S Li, CW Pui, D Liu, L Shen, Y Lin, N Sun, DZ Pan
Proceedings of the 2019 International Symposium on Physical Design, 19-26, 2019
34 2019 Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict Y Lin, B Yu, B Xu, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
34 2017 Closing the design loop: Bayesian optimization assisted hierarchical analog layout synthesis M Liu, K Zhu, X Tang, B Xu, W Shi, N Sun, DZ Pan
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
29 2020 Improving Google flu trends estimates for the United States through transformation LJ Martin, B Xu, Y Yasui
PloS one 9 (12), e109209, 2014
27 2014 A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time A Mukherjee, M Gandara, B Xu, S Li, L Shen, X Tang, D Pan, N Sun
IEEE Solid-State Circuits Letters 2 (1), 1-4, 2019
16 2019 A 60-fJ/step 11-ENOB VCO-based CTDSM synthesized from digital standard cell library S Li, B Xu, DZ Pan, N Sun
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
15 2019 A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure S Li, W Zhao, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-3, 2019
15 2019 Exploiting wavelength division multiplexing for optical logic synthesis Z Zhao, D Liu, Z Ying, B Xu, C Feng, RT Chen, DZ Pan
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
13 2019 Analog placement constraint extraction and exploration with the application to layout retargeting B Xu, B Basaran, M Su, DZ Pan
Proceedings of the 2018 International Symposium on Physical Design, 98-105, 2018
12 2018 Layout Automation for Analog and Mixed-Signal Integrated Circuits B Xu
The University of Texas at Austin, 2019
2 2019 
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinBestätigte E-Mail-Adresse bei ece.utexas.edu
