Kaushik Roy
Kaushik Roy
Professor of Electrical and Computer Engineering, Purdue University
Bestätigte E-Mail-Adresse bei purdue.edu - Startseite
Zitiert von
Zitiert von
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
K Roy, S Mukhopadhyay, H Mahmoodi-Meimand
Proceedings of the IEEE 91 (2), 305-327, 2003
Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates
Q Cao, H Kim, N Pimparkar, JP Kulkarni, C Wang, M Shim, K Roy, ...
Nature 454 (7203), 495-500, 2008
Gated-Vdd a circuit technique to reduce leakage in deep-submicron cache memories
M Powell, SH Yang, B Falsafi, K Roy, TN Vijaykumar
Proceedings of the 2000 international symposium on Low power electronics and …, 2000
Low-power CMOS VLSI circuit design
K Roy, SC Prasad
John Wiley & Sons, 2009
Low-power digital signal processing using approximate adders
V Gupta, D Mohapatra, A Raghunathan, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
S Mukhopadhyay, H Mahmoodi, K Roy
IEEE transactions on computer-aided design of integrated circuits and …, 2005
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009
A 160 mV robust Schmitt trigger based subthreshold SRAM
JP Kulkarni, K Kim, K Roy
IEEE Journal of Solid-State Circuits 42 (10), 2303-2313, 2007
Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks
Z Chen, M Johnson, L Wei, W Roy
Proceedings. 1998 International Symposium on Low Power Electronics and …, 1998
IMPACT: IMPrecise adders for low-power approximate computing
V Gupta, D Mohapatra, SP Park, A Raghunathan, K Roy
IEEE/ACM International Symposium on Low Power Electronics and Design, 409-414, 2011
Analysis and characterization of inherent application resilience for approximate computing
VK Chippa, ST Chakradhar, K Roy, A Raghunathan
Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013
Design and optimization of dual-threshold circuits for low-voltage low-power applications
L Wei, Z Chen, K Roy, MC Johnson, Y Ye, VK De
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (1), 16-24, 1999
Leakage control with efficient use of transistor stacks in single threshold CMOS
MC Johnson, D Somasekhar, LY Chiou, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (1), 1-5, 2002
Robust subthreshold logic for ultra-low power operation
H Soeleman, K Roy, BC Paul
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 90-99, 2001
Reducing set-associative cache energy via way-prediction and selective direct-mapping
MD Powell, A Agarwal, TN Vijaykumar, B Falsafi, K Roy
Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001
Impact of NBTI on the temporal performance degradation of digital circuits
BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy
IEEE Electron Device Letters 26 (8), 560-562, 2005
SALSA: Systematic logic synthesis of approximate circuits
S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan
DAC Design Automation Conference 2012, 796-801, 2012
An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches
S Yang, MD Powell, B Falsafi, K Roy, TN Vijaykumar
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
Design and optimization of low voltage high performance dual threshold CMOS circuits
L Wei, Z Chen, M Johnson, K Roy, V De
Proceedings of the 35th annual Design Automation Conference, 489-494, 1998
Quality programmable vector processors for approximate computing
S Venkataramani, VK Chippa, ST Chakradhar, K Roy, A Raghunathan
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
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