A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs N Da Dalt
IEEE Transactions on Circuits and Systems I: Regular Papers 52 (1), 21-31, 2005
205 2005 On the jitter requirements of the sampling clock for analog-to-digital converters N Da Dalt, M Harteneck, C Sandner, A Wiesbauer
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2002
171 2002 Linearized analysis of a digital bang-bang PLL and its validity limits applied to jitter transfer and jitter generation N Da Dalt
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (11), 3663-3675, 2008
132 2008 Markov chains-based derivation of the phase detector gain in bang-bang PLLs N Da Dalt
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (11), 1195-1199, 2006
120 2006 A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS N Da Dalt, E Thaller, P Gregorius, L Gazsi
IEEE Journal of Solid-State Circuits 40 (7), 1482-1490, 2005
100 2005 A 1.4 ps rms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS W Grollitsch, R Nonis, N Da Dalt
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 …, 2010
98 2010 Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture R Nonis, N Da Dalt, P Palestri, L Selmi
IEEE Journal of Solid-State Circuits 40 (6), 1303-1309, 2005
88 2005 Understanding jitter and phase noise: A circuits and systems perspective N Da Dalt, A Sheikholeslami
Cambridge University Press, 2018
86 2018 A sub-psec jitter PLL for clock generation in 0.12um digital CMOS N Da Dalt, C Sandner
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th …, 2002
75 * 2002 digPLL-Lite: A low-complexity, low-jitter fractional-N digital PLL architecture R Nonis, W Grollitsch, T Santa, D Cherniak, N Da Dalt
IEEE journal of solid-state circuits 48 (12), 3134-3145, 2013
74 2013 Multi-mode/Multi-band RF transceivers for wireless communications: Advanced techniques, Architectures, and Trends G Hueber, RB Staszewski
John Wiley & Sons, 2011
73 2011 A 10b 10GHz digitally controlled LC oscillator in 65nm CMOS D Dalt
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
64 2006 A 0.06 mm S Dal Toso, A Bevilacqua, M Tiebout, N Da Dalt, A Gerosa, A Neviani
IEEE Journal of Solid-State Circuits 45 (7), 1295-1304, 2010
51 2010 An Analysis of Phase Noise in Realigned VCOs N Da Dalt
Circuits and Systems II: Express Briefs, IEEE Transactions on 61 (3), 2014
47 2014 A fully integrated 13 GHz/spl Delta//spl Sigma/fractional-n PLL in 0.13/spl mu/m CMOS M Tiebout, C Sandner, HD Wohlmuth, N Da Dalt, E Thaller
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004
43 2004 Theory and implementation of digital bang-bang frequency synthesizers for high speed serial data communications N Da Dalt
Diplom-Ingenieur Dissertation, 2007
38 2007 Method and device for generating a clock signal using a phase difference signal and a feedback signal N Da Dalt, P Gregorius
US Patent 7,282,999, 2007
36 2007 Dynamics of induced modulational instability in waveguides with saturable nonlinearity N Da Dalt, C De Angelis, GF Nalesso, M Santagiustina
Optics communications 121 (1-3), 69-72, 1995
34 1995 Digital phase-locked loop N Da Dalt, C Sandner
US Patent 6,970,046, 2005
32 2005 An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Dal Toso, A Bevilacqua, M Tiebout, N Da Dalt, A Gerosa, A Neviani
IEEE Transactions on Microwave Theory and Techniques 58 (7), 1686-1695, 2010
29 2010 
Ali SheikholeslamiProfessor of Electrical and Computer Engineering, University of TorontoBestätigte E-Mail-Adresse bei eecg.utoronto.ca
