Sandeep Kumar Goel
Sandeep Kumar Goel
Academician/Director, TSMC
Bestätigte E-Mail-Adresse bei - Startseite
Zitiert von
Zitiert von
Design for debug: Catching design errors in digital chips
B Vermeulen, SK Goel
IEEE Design & Test of Computers 19 (03), 37-45, 2002
Wrapper design for embedded core test
EJ Marinissen, SK Goel, M Lousberg
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
Core-based scan architecture for silicon debug
B Vermeulen, T Waayers, SK Goel
Proceedings. International Test Conference, 638-647, 2002
Effective and efficient test architecture design for SOCs
SK Goel, EJ Marinissen
Proceedings. International Test Conference, 529-538, 2002
Automatic generation of breakpoint hardware for silicon debug
B Vermeulen, MZ Urfianto, SK Goel
Proceedings of the 41st annual Design Automation Conference, 514-517, 2004
SOC test architecture design for efficient utilization of test bandwidth
SK Goel, EJ Marinissen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003
Multi-dimensional integrated circuit structures and methods of forming the same
M Semmelmeyer, SK Goel
US Patent 8,686,570, 2014
Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs
B Noia, K Chakrabarty, SK Goel, EJ Marinissen, J Verbree
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
Subgoal discovery for hierarchical reinforcement learning using learned policies
S Goel, M Huber
FLAIRS conference, 346-350, 2003
Test-architecture optimization for TSV-based 3D stacked ICs
B Noia, SK Goel, K Chakrabarty, EJ Marinissen, J Verbree
2010 15th IEEE European Test Symposium, 24-29, 2010
A 7-nm 4-GHz Arm¹-core-based CoWoS¹ chiplet design for high-performance computing
MS Lin, TC Huang, CC Tsai, KH Tam, KCH Hsieh, CF Chen, WH Huang, ...
IEEE Journal of Solid-State Circuits 55 (4), 956-966, 2020
Post-bond testing of 2.5 D-SICs and 3D-SICs containing a passive silicon interposer base
CC Chi, EJ Marinissen, SK Goel, CW Wu
2011 IEEE International Test Conference, 1-10, 2011
Testing of SoCs with hierarchical cores: common fallacies, test access optimization, and test scheduling
S Goel, EJ Marinissen, A Sehgal, K Chakrabarty
IEEE Transactions on Computers 58 (3), 409-423, 2008
Effective and efficient test pattern generation for small delay defect
SK Goel, N Devta-Prasanna, RP Turakhia
2009 27th IEEE VLSI Test Symposium, 111-116, 2009
Test infrastructure design for the Nexperia/spl trade/home platform PNX8550 system chip
SK Goel, K Chiu, EJ Marinissen, T Nguyen, S Oostdijk
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
IEEE P1500-compliant test wrapper design for hierarchical cores
A Sehgal, SK Goel, EJ Marinissen, K Chakrabarty
2004 International Conferce on Test, 1203-1212, 2004
Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints
V Iyengar, SK Goel, EJ Marinissen, K Chakrabarty
Proceedings. International Test Conference, 1159-1168, 2002
Cluster-based test architecture design for system-on-chip
SK Goel, EJ Marinissen
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 259-264, 2002
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
S Deutsch, B Keller, V Chickermane, S Mukherjee, N Sood, SK Goel, ...
2012 IEEE International Test Conference, 1-10, 2012
Control-aware test architecture design for modular SOC testing
SK Goel, EJ Marinissen
The Eighth IEEE European Test Workshop, 2003. Proceedings., 57-62, 2003
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