| Towards the hierarchical design of multilayer QCA logic circuit B Sen, A Nag, A De, BK Sikdar Journal of Computational Science 11, 233-244, 2015 | 49 | 2015 |
| FIXER: Flow integrity extensions for embedded RISC-V A De, A Basu, S Ghosh, T Jaeger 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 348-353, 2019 | 46* | 2019 |
| Security and privacy threats to on-chip non-volatile memories and countermeasures S Ghosh, MNI Khan, A De, JW Jang 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016 | 33 | 2016 |
| Hardware assisted buffer protection mechanisms for embedded RISC-V A De, A Basu, S Ghosh, T Jaeger IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 25 | 2020 |
| Power side channel attack analysis and detection N Gattu, MNI Khan, A De, S Ghosh Proceedings of the 39th International Conference on Computer-Aided Design, 1-7, 2020 | 23* | 2020 |
| HarTBleed: Using hardware Trojans for data leakage exploits A De, MNI Khan, K Nagarajan, S Ghosh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 968-979, 2020 | 23 | 2020 |
| Cache-out: Leaking cache memory using hardware trojan MNI Khan, A De, S Ghosh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 19 | 2020 |
| Replacing eFlash with STTRAM in IoTs: security challenges and solutions A De, MNI Khan, J Park, S Ghosh Journal of Hardware and Systems Security 1, 328-339, 2017 | 17* | 2017 |
| Multilayer design of QCA multiplexer B Sen, A Nag, A De, BK Sikdar 2013 Annual IEEE India Conference (INDICON), 1-6, 2013 | 16 | 2013 |
| Preventing reverse engineering using threshold voltage defined multi-input camouflaged gates A De, S Ghosh 2017 IEEE International Symposium on Technologies for Homeland Security (HST …, 2017 | 14 | 2017 |
| TrappeD: DRAM trojan designs for information leakage and fault injection attacks AD Karthikeyan Nagarajan Microprocessor test and validation, 2019 | 8* | 2019 |
| Armor PLC: A platform for cyber security threats assessments for PLCs W Zhang, Y Jiao, D Wu, S Srinivasa, A De, S Ghosh, P Liu Procedia Manufacturing 39, 270-278, 2019 | 8 | 2019 |
| SecNVM: Power side-channel elimination using on-chip capacitors for highly secure emerging NVM K Nagarajan, FU Ahmed, MNI Khan, A De, MH Chowdhury, S Ghosh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (8 …, 2021 | 6 | 2021 |
| Cache bypassing and checkpointing to circumvent data security attacks on sttram N Rathi, A De, H Naeimi, S Ghosh arXiv preprint arXiv:1603.06227, 2016 | 6 | 2016 |
| Threshold-defined logic and interconnect for protection against reverse engineering JW Jang, A De, D Vontela, I Nirmala, S Ghosh, A Iyengar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 5 | 2018 |
| CTCG: Charge-trap based camouflaged gates for reverse engineering prevention A De, A Iyengar, MNI Khan, SH Lin, S Thirumala, S Ghosh, S Gupta 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 5 | 2018 |
| HeapSafe: securing unprotected heaps in RISC-V A De, S Ghosh 2022 35th International Conference on VLSI Design and 2022 21st …, 2022 | 4 | 2022 |
| Recent advances in emerging technology-based security primitives, attacks and mitigation K Nagarajan, A De, SS Ensan, A Ash-Saki, MNI Khan, S Ghosh 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems …, 2020 | 2 | 2020 |
| Hands-On Cybersecurity Curriculum using a Modular Training Kit A De | 2 | 2020 |
| Threshold voltage defined multi-input complex gates A De, S Ghosh 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017 | 1 | 2017 |
Swaroop GhoshPennsylvania State UniversityBestätigte E-Mail-Adresse bei psu.edu
